[3/3] ARM: dts: Add g3d bus nodes using VDD_INT for Exynos542x SoC
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Message ID 20181123094413.1108-3-linux.amoon@gmail.com
State New
Headers show
Series
  • [1/3] clk: samsung: exynos5420: add VPLL rate table for g3d clock
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Commit Message

Anand Moon Nov. 23, 2018, 9:44 a.m. UTC
Add missing Netwwork on chip for g3d bus node using VDD_INI
for Exynos542x SoC.

- CLK_DOUT_ACLK_G3D for G3D's AXI

Cc: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/boot/dts/exynos5420.dtsi             | 57 +++++++++++++++++--
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi |  5 ++
 2 files changed, 56 insertions(+), 6 deletions(-)

Comments

Chanwoo Choi Nov. 26, 2018, 7:37 a.m. UTC | #1
Hi Anand,

CLK_DOUT_ACLK_G3D is the clock for GPU h/w and it requires the buck4_reg("vdd_g3d").

bus_wcore uses the buck3_reg("vdd_int"). bus_wcore and bus_g3d don't share the 
same voltage line. It is wrong to make 'bus_g3d' as the child of 'bus_wcore'
because of using the different regulator.

CLK_DOUT_ACLK_G3D and buck4_reg should be controlled from MALI driver 
with DEVFREQ framework. Unfortunately, MALI driver is not posted to mainline.


On 2018년 11월 23일 18:44, Anand Moon wrote:
> Add missing Netwwork on chip for g3d bus node using VDD_INI
> for Exynos542x SoC.
> 
> - CLK_DOUT_ACLK_G3D for G3D's AXI
> 
> Cc: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  arch/arm/boot/dts/exynos5420.dtsi             | 57 +++++++++++++++++--
>  arch/arm/boot/dts/exynos5422-odroid-core.dtsi |  5 ++
>  2 files changed, 56 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index aaff15880761..bc7203bb1282 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -1047,6 +1047,14 @@
>  			status = "disabled";
>  		};
>  
> +		bus_g3d: bus_g3d {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&clock CLK_DOUT_ACLK_G3D>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_g3d_opp_table>;
> +			status = "disabled";
> +		};
> +
>  		bus_jpeg: bus_jpeg {
>  			compatible = "samsung,exynos-bus";
>  			clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
> @@ -1245,7 +1253,44 @@
>  			};
>  		};
>  
> -		bus_jpeg_opp_table: opp_table11 {
> +		bus_g3d_opp_table: opp_table11 {
> +			compatible = "operating-points-v2";
> +
> +			opp@600000000 {
> +				opp-hz = /bits/ 64 <600000000>;
> +				opp-microvolt = <1025000>;
> +			};
> +			opp@543000000 {
> +				opp-hz = /bits/ 64 <543000000>;
> +				opp-microvolt = <987500>;
> +			};
> +			opp@480000000 {
> +				opp-hz = /bits/ 64 <480000000>;
> +				opp-microvolt = <950000>;
> +			};
> +			opp@420000000 {
> +				opp-hz = /bits/ 64 <420000000>;
> +				opp-microvolt = <937500>;
> +			};
> +			opp@350000000 {
> +				opp-hz = /bits/ 64 <350000000>;
> +				opp-microvolt = <900000>;
> +			};
> +			opp@266000000 {
> +				opp-hz = /bits/ 64 <266000000>;
> +				opp-microvolt = <862500>;
> +			};
> +			opp@177000000 {
> +				opp-hz = /bits/ 64 <177000000>;
> +				opp-microvolt = <862500>;
> +			};
> +			opp@100000000 {
> +				opp-hz = /bits/ 64 <100000000>;
> +				opp-microvolt = <862500>;
> +			};
> +		};
> +
> +		bus_jpeg_opp_table: opp_table12 {
>  			compatible = "operating-points-v2";
>  
>  			opp00 {
> @@ -1262,7 +1307,7 @@
>  			};
>  		};
>  
> -		bus_jpeg_apb_opp_table: opp_table12 {
> +		bus_jpeg_apb_opp_table: opp_table13 {
>  			compatible = "operating-points-v2";
>  
>  			opp00 {
> @@ -1279,7 +1324,7 @@
>  			};
>  		};
>  
> -		bus_disp1_fimd_opp_table: opp_table13 {
> +		bus_disp1_fimd_opp_table: opp_table14 {
>  			compatible = "operating-points-v2";
>  
>  			opp00 {
> @@ -1290,7 +1335,7 @@
>  			};
>  		};
>  
> -		bus_disp1_opp_table: opp_table14 {
> +		bus_disp1_opp_table: opp_table15 {
>  			compatible = "operating-points-v2";
>  
>  			opp00 {
> @@ -1304,7 +1349,7 @@
>  			};
>  		};
>  
> -		bus_gscl_opp_table: opp_table15 {
> +		bus_gscl_opp_table: opp_table16 {
>  			compatible = "operating-points-v2";
>  
>  			opp00 {
> @@ -1318,7 +1363,7 @@
>  			};
>  		};
>  
> -		bus_mscl_opp_table: opp_table16 {
> +		bus_mscl_opp_table: opp_table17 {
>  			compatible = "operating-points-v2";
>  
>  			opp00 {
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index 2fac4baf1eb4..6e39e4594502 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -89,6 +89,11 @@
>  	status = "okay";
>  };
>  
> +&bus_g3d {
> +	devfreq = <&bus_wcore>;
> +	status = "okay";
> +};
> +
>  &bus_jpeg {
>  	devfreq = <&bus_wcore>;
>  	status = "okay";
>
Anand Moon Nov. 26, 2018, 8:49 a.m. UTC | #2
Hi Chanwoo,

On Mon, 26 Nov 2018 at 13:08, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>
> Hi Anand,
>
> CLK_DOUT_ACLK_G3D is the clock for GPU h/w and it requires the buck4_reg("vdd_g3d").
>
> bus_wcore uses the buck3_reg("vdd_int"). bus_wcore and bus_g3d don't share the
> same voltage line. It is wrong to make 'bus_g3d' as the child of 'bus_wcore'
> because of using the different regulator.
>
> CLK_DOUT_ACLK_G3D and buck4_reg should be controlled from MALI driver
> with DEVFREQ framework. Unfortunately, MALI driver is not posted to mainline.
>
>

Thanks for your clarification, I missed this point. mali gpu is linked
to buck4_reg
Next time I will ask for the expert how to proceed on some changes.

Best Regards
-Anand

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index aaff15880761..bc7203bb1282 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1047,6 +1047,14 @@ 
 			status = "disabled";
 		};
 
+		bus_g3d: bus_g3d {
+			compatible = "samsung,exynos-bus";
+			clocks = <&clock CLK_DOUT_ACLK_G3D>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_g3d_opp_table>;
+			status = "disabled";
+		};
+
 		bus_jpeg: bus_jpeg {
 			compatible = "samsung,exynos-bus";
 			clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
@@ -1245,7 +1253,44 @@ 
 			};
 		};
 
-		bus_jpeg_opp_table: opp_table11 {
+		bus_g3d_opp_table: opp_table11 {
+			compatible = "operating-points-v2";
+
+			opp@600000000 {
+				opp-hz = /bits/ 64 <600000000>;
+				opp-microvolt = <1025000>;
+			};
+			opp@543000000 {
+				opp-hz = /bits/ 64 <543000000>;
+				opp-microvolt = <987500>;
+			};
+			opp@480000000 {
+				opp-hz = /bits/ 64 <480000000>;
+				opp-microvolt = <950000>;
+			};
+			opp@420000000 {
+				opp-hz = /bits/ 64 <420000000>;
+				opp-microvolt = <937500>;
+			};
+			opp@350000000 {
+				opp-hz = /bits/ 64 <350000000>;
+				opp-microvolt = <900000>;
+			};
+			opp@266000000 {
+				opp-hz = /bits/ 64 <266000000>;
+				opp-microvolt = <862500>;
+			};
+			opp@177000000 {
+				opp-hz = /bits/ 64 <177000000>;
+				opp-microvolt = <862500>;
+			};
+			opp@100000000 {
+				opp-hz = /bits/ 64 <100000000>;
+				opp-microvolt = <862500>;
+			};
+		};
+
+		bus_jpeg_opp_table: opp_table12 {
 			compatible = "operating-points-v2";
 
 			opp00 {
@@ -1262,7 +1307,7 @@ 
 			};
 		};
 
-		bus_jpeg_apb_opp_table: opp_table12 {
+		bus_jpeg_apb_opp_table: opp_table13 {
 			compatible = "operating-points-v2";
 
 			opp00 {
@@ -1279,7 +1324,7 @@ 
 			};
 		};
 
-		bus_disp1_fimd_opp_table: opp_table13 {
+		bus_disp1_fimd_opp_table: opp_table14 {
 			compatible = "operating-points-v2";
 
 			opp00 {
@@ -1290,7 +1335,7 @@ 
 			};
 		};
 
-		bus_disp1_opp_table: opp_table14 {
+		bus_disp1_opp_table: opp_table15 {
 			compatible = "operating-points-v2";
 
 			opp00 {
@@ -1304,7 +1349,7 @@ 
 			};
 		};
 
-		bus_gscl_opp_table: opp_table15 {
+		bus_gscl_opp_table: opp_table16 {
 			compatible = "operating-points-v2";
 
 			opp00 {
@@ -1318,7 +1363,7 @@ 
 			};
 		};
 
-		bus_mscl_opp_table: opp_table16 {
+		bus_mscl_opp_table: opp_table17 {
 			compatible = "operating-points-v2";
 
 			opp00 {
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 2fac4baf1eb4..6e39e4594502 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -89,6 +89,11 @@ 
 	status = "okay";
 };
 
+&bus_g3d {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
 &bus_jpeg {
 	devfreq = <&bus_wcore>;
 	status = "okay";