ARM: tegra: Add VIC on Tegra124
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Message ID 20181123120403.16244-1-thierry.reding@gmail.com
State New
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Series
  • ARM: tegra: Add VIC on Tegra124
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Commit Message

Thierry Reding Nov. 23, 2018, 12:04 p.m. UTC
From: Thierry Reding <treding@nvidia.com>

The Video Image Compositor can be used to perform a variety of image
operations. Add a device tree node for it, so that it can be exposed
as a host1x channel to userspace.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm/boot/dts/tegra124.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Jon Hunter Nov. 29, 2018, 1:34 p.m. UTC | #1
On 23/11/2018 12:04, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The Video Image Compositor can be used to perform a variety of image
> operations. Add a device tree node for it, so that it can be exposed
> as a host1x channel to userspace.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm/boot/dts/tegra124.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 183c5acafb22..b113e47b2b2a 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -140,6 +140,18 @@
>  			status = "disabled";
>  		};
>  
> +		vic@54340000 {
> +			compatible = "nvidia,tegra124-vic";
> +			reg = <0x0 0x54340000 0x0 0x00040000>;
> +			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&tegra_car TEGRA124_CLK_VIC03>;
> +			clock-names = "vic";
> +			resets = <&tegra_car 178>;
> +			reset-names = "vic";
> +
> +			iommus = <&mc TEGRA_SWGROUP_VIC>;
> +		};
> +
>  		sor@54540000 {
>  			compatible = "nvidia,tegra124-sor";
>  			reg = <0x0 0x54540000 0x0 0x00040000>;
> 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 183c5acafb22..b113e47b2b2a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -140,6 +140,18 @@ 
 			status = "disabled";
 		};
 
+		vic@54340000 {
+			compatible = "nvidia,tegra124-vic";
+			reg = <0x0 0x54340000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA124_CLK_VIC03>;
+			clock-names = "vic";
+			resets = <&tegra_car 178>;
+			reset-names = "vic";
+
+			iommus = <&mc TEGRA_SWGROUP_VIC>;
+		};
+
 		sor@54540000 {
 			compatible = "nvidia,tegra124-sor";
 			reg = <0x0 0x54540000 0x0 0x00040000>;