| Message ID | 20181123123138.20739-2-thierry.reding@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/7] gpu: host1x: Resize channel register region on Tegra186 and later | expand |
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> On 23.11.2018 14:31, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The number of syncpoints on Tegra186 is 576 and therefore no longer fits > into 8 bits. Increase the size of the syncpoint ID field to 10 in order > to accomodate all syncpoints. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/gpu/host1x/hw/hw_host1x06_uclass.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/host1x/hw/hw_host1x06_uclass.h b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h > index 4457486c72b0..e599e15bf999 100644 > --- a/drivers/gpu/host1x/hw/hw_host1x06_uclass.h > +++ b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h > @@ -59,7 +59,7 @@ static inline u32 host1x_uclass_incr_syncpt_r(void) > host1x_uclass_incr_syncpt_r() > static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) > { > - return (v & 0xff) << 8; > + return (v & 0xff) << 10; > } > #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ > host1x_uclass_incr_syncpt_cond_f(v) >
diff --git a/drivers/gpu/host1x/hw/hw_host1x06_uclass.h b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h index 4457486c72b0..e599e15bf999 100644 --- a/drivers/gpu/host1x/hw/hw_host1x06_uclass.h +++ b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h @@ -59,7 +59,7 @@ static inline u32 host1x_uclass_incr_syncpt_r(void) host1x_uclass_incr_syncpt_r() static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xff) << 10; } #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ host1x_uclass_incr_syncpt_cond_f(v)