| Message ID | 20181129022431.18732-1-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/i915/cnl: Fix the formulae for register offsets | expand |
On Wed, 28 Nov 2018, Radhakrishna Sripada <radhakrishna.sripada@intel.com> wrote: > For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well > for higher slices. > > v2: Use _PICK instead of formulae(Jani) > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Lucs De Marchi <lucas.demarchi@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++++++++++++++++++++++++++++----- > 1 file changed, 48 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 47baf2fe8f71..3b8ee7dd9b62 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8662,18 +8662,60 @@ enum { > #define CHV_EU311_PG_ENABLE (1 << 1) > > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) > -#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ > - ((slice) % 3) * 0x4) > + > +#define _CNL_SLICE0_PGCTL_ACK 0x804c > +#define _CNL_SLICE1_PGCTL_ACK 0x8050 > +#define _CNL_SLICE2_PGCTL_ACK 0x8054 > +#define _CNL_SLICE3_PGCTL_ACK 0x8080 > +#define _CNL_SLICE4_PGCTL_ACK 0x8084 > +#define _CNL_SLICE5_PGCTL_ACK 0x8088 > + Superfluous newline. > +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(_PICK(slice, \ > + _CNL_SLICE0_PGCTL_ACK, \ > + _CNL_SLICE1_PGCTL_ACK, \ > + _CNL_SLICE2_PGCTL_ACK, \ > + _CNL_SLICE3_PGCTL_ACK, \ > + _CNL_SLICE4_PGCTL_ACK, \ > + _CNL_SLICE5_PGCTL_ACK)) > + > #define GEN9_PGCTL_SLICE_ACK (1 << 0) > #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) > #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) > > #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) > -#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ > - ((slice) % 3) * 0x8) > + > +#define _CNL_SLICE0_SS01_EU_PGCTL_ACK 0x805c > +#define _CNL_SLICE1_SS01_EU_PGCTL_ACK 0x8064 > +#define _CNL_SLICE2_SS01_EU_PGCTL_ACK 0x806c > +#define _CNL_SLICE3_SS01_EU_PGCTL_ACK 0x808c > +#define _CNL_SLICE4_SS01_EU_PGCTL_ACK 0x8094 > +#define _CNL_SLICE5_SS01_EU_PGCTL_ACK 0x809c > + Superfluous newline. > +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \ > + _CNL_SLICE0_SS01_EU_PGCTL_ACK, \ > + _CNL_SLICE1_SS01_EU_PGCTL_ACK, \ > + _CNL_SLICE2_SS01_EU_PGCTL_ACK, \ > + _CNL_SLICE3_SS01_EU_PGCTL_ACK, \ > + _CNL_SLICE4_SS01_EU_PGCTL_ACK, \ > + _CNL_SLICE5_SS01_EU_PGCTL_ACK)) > + > #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) > -#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ > - ((slice) % 3) * 0x8) > + Superfluous newline. Otherwise looks good, I didn't much care for the formulas for calculating register offsets. With the extra newlines removed, Reviewed-by: Jani Nikula <jani.nikula@intel.com> > +#define _CNL_SLICE0_SS23_EU_PGCTL_ACK 0x8060 > +#define _CNL_SLICE1_SS23_EU_PGCTL_ACK 0x8068 > +#define _CNL_SLICE2_SS23_EU_PGCTL_ACK 0x8070 > +#define _CNL_SLICE3_SS23_EU_PGCTL_ACK 0x8090 > +#define _CNL_SLICE4_SS23_EU_PGCTL_ACK 0x8098 > +#define _CNL_SLICE5_SS23_EU_PGCTL_ACK 0x80a0 > + > +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \ > + _CNL_SLICE0_SS23_EU_PGCTL_ACK, \ > + _CNL_SLICE1_SS23_EU_PGCTL_ACK, \ > + _CNL_SLICE2_SS23_EU_PGCTL_ACK, \ > + _CNL_SLICE3_SS23_EU_PGCTL_ACK, \ > + _CNL_SLICE4_SS23_EU_PGCTL_ACK, \ > + _CNL_SLICE5_SS23_EU_PGCTL_ACK)) > + > #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) > #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) > #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 47baf2fe8f71..3b8ee7dd9b62 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8662,18 +8662,60 @@ enum { #define CHV_EU311_PG_ENABLE (1 << 1) #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) -#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ - ((slice) % 3) * 0x4) + +#define _CNL_SLICE0_PGCTL_ACK 0x804c +#define _CNL_SLICE1_PGCTL_ACK 0x8050 +#define _CNL_SLICE2_PGCTL_ACK 0x8054 +#define _CNL_SLICE3_PGCTL_ACK 0x8080 +#define _CNL_SLICE4_PGCTL_ACK 0x8084 +#define _CNL_SLICE5_PGCTL_ACK 0x8088 + +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(_PICK(slice, \ + _CNL_SLICE0_PGCTL_ACK, \ + _CNL_SLICE1_PGCTL_ACK, \ + _CNL_SLICE2_PGCTL_ACK, \ + _CNL_SLICE3_PGCTL_ACK, \ + _CNL_SLICE4_PGCTL_ACK, \ + _CNL_SLICE5_PGCTL_ACK)) + #define GEN9_PGCTL_SLICE_ACK (1 << 0) #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) -#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ - ((slice) % 3) * 0x8) + +#define _CNL_SLICE0_SS01_EU_PGCTL_ACK 0x805c +#define _CNL_SLICE1_SS01_EU_PGCTL_ACK 0x8064 +#define _CNL_SLICE2_SS01_EU_PGCTL_ACK 0x806c +#define _CNL_SLICE3_SS01_EU_PGCTL_ACK 0x808c +#define _CNL_SLICE4_SS01_EU_PGCTL_ACK 0x8094 +#define _CNL_SLICE5_SS01_EU_PGCTL_ACK 0x809c + +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \ + _CNL_SLICE0_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE1_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE2_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE3_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE4_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE5_SS01_EU_PGCTL_ACK)) + #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) -#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ - ((slice) % 3) * 0x8) + +#define _CNL_SLICE0_SS23_EU_PGCTL_ACK 0x8060 +#define _CNL_SLICE1_SS23_EU_PGCTL_ACK 0x8068 +#define _CNL_SLICE2_SS23_EU_PGCTL_ACK 0x8070 +#define _CNL_SLICE3_SS23_EU_PGCTL_ACK 0x8090 +#define _CNL_SLICE4_SS23_EU_PGCTL_ACK 0x8098 +#define _CNL_SLICE5_SS23_EU_PGCTL_ACK 0x80a0 + +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \ + _CNL_SLICE0_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE1_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE2_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE3_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE4_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE5_SS23_EU_PGCTL_ACK)) + #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well for higher slices. v2: Use _PICK instead of formulae(Jani) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Lucs De Marchi <lucas.demarchi@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 6 deletions(-)