Message ID | 1543573889-8355-1-git-send-email-festevam@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2] ARM: dts: imx7d-pico: Describe the Wifi clock | expand |
On Fri, Nov 30, 2018 at 08:31:29AM -0200, Fabio Estevam wrote: > The Wifi chip should be clocked by a 32kHz clock coming from i.MX7D > CLKO2 output pin, so describe the pinmux and clock hierarchy in the > device tree to allow the Wifi chip to be properly clocked. > > Managed to successfully test Wifi with such change. Used the standard > nvram.txt file provided by TechNexion, which selects an external 32kHz > clock for the Wifi chip by default. > > Fixes: 99a52450c707 ("ARM: dts: imx7d-pico: Add Wifi support") > Suggested-by: Arend van Spriel <arend.vanspriel@broadcom.com> > Tested-by: Otavio Salvador <otavio@ossystems.com.br> > Signed-off-by: Fabio Estevam <festevam@gmail.com> Okay, replaced the RFC patch with this one. Shawn
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index 4846df0..934a019 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -101,6 +101,19 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; + clock-names = "ext_clock"; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, + <&clks IMX7D_CLKO2_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_CKIL>; + assigned-clock-rates = <0>, <32768>; }; &i2c4 { @@ -200,12 +213,13 @@ &usdhc2 { /* Wifi SDIO */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>; no-1-8-v; non-removable; keep-power-in-suspend; wakeup-source; vmmc-supply = <®_ap6212>; + mmc-pwrseq = <&usdhc2_pwrseq>; status = "okay"; }; @@ -302,6 +316,12 @@ }; &iomuxc_lpsr { + pinctrl_wifi_clk: wificlkgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74