[1/6] drm/v3d: Document cache flushing ABI.
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Message ID 20181201005759.28093-1-eric@anholt.net
State New
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  • [1/6] drm/v3d: Document cache flushing ABI.
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Commit Message

Eric Anholt Dec. 1, 2018, 12:57 a.m. UTC
Right now, userspace doesn't do any L2T writes, but we should lay out
our expectations for how it works.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 include/uapi/drm/v3d_drm.h | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Dave Emett Dec. 3, 2018, 5:22 p.m. UTC | #1
> + * The caches (L1T, slice, and L2T) will be flushed before the job
> + * executes.  The TLB writes are guaranteed to have been flushed by

I would say before *each* job executes, as the caches are flushed
before both bin and render.
I wouldn't say "the caches" as not all of the V3D caches are flushed
before executing a control list. In particular, the VCD cache is not
cleared by the kernel driver (not even sure if there is a register
interface to do this); it is expected that the control list will do
this itself (using the CLEAR_VCD_CACHE instruction).
On 3.3 and earlier there is a separate L2C for instructions/uniforms
and a GCA. These do need to be flushed, and it looks like they are, so
they should be mentioned here.
Dave Emett Dec. 3, 2018, 5:28 p.m. UTC | #2
On Mon, 3 Dec 2018 at 17:22, Dave Emett <david.emett@broadcom.com> wrote:
>
> > + * The caches (L1T, slice, and L2T) will be flushed before the job
> > + * executes.  The TLB writes are guaranteed to have been flushed by
>
> I would say before *each* job executes, as the caches are flushed
> before both bin and render.
> I wouldn't say "the caches" as not all of the V3D caches are flushed
> before executing a control list. In particular, the VCD cache is not
> cleared by the kernel driver (not even sure if there is a register
> interface to do this); it is expected that the control list will do
> this itself (using the CLEAR_VCD_CACHE instruction).
> On 3.3 and earlier there is a separate L2C for instructions/uniforms
> and a GCA. These do need to be flushed, and it looks like they are, so
> they should be mentioned here.

Correction: on *3.2* and earlier there is a separate L2C for
instructions/uniforms. On 3.3 and earlier there is a GCA.

It looks like we're currently unconditionally writing the L2C clear
registers. We should really only be doing this on 3.2 and earlier.
Eric Anholt Dec. 3, 2018, 8:39 p.m. UTC | #3
Dave Emett <david.emett@broadcom.com> writes:

> On Mon, 3 Dec 2018 at 17:22, Dave Emett <david.emett@broadcom.com> wrote:
>>
>> > + * The caches (L1T, slice, and L2T) will be flushed before the job
>> > + * executes.  The TLB writes are guaranteed to have been flushed by
>>
>> I would say before *each* job executes, as the caches are flushed
>> before both bin and render.
>> I wouldn't say "the caches" as not all of the V3D caches are flushed
>> before executing a control list. In particular, the VCD cache is not
>> cleared by the kernel driver (not even sure if there is a register
>> interface to do this); it is expected that the control list will do
>> this itself (using the CLEAR_VCD_CACHE instruction).
>> On 3.3 and earlier there is a separate L2C for instructions/uniforms
>> and a GCA. These do need to be flushed, and it looks like they are, so
>> they should be mentioned here.
>
> Correction: on *3.2* and earlier there is a separate L2C for
> instructions/uniforms. On 3.3 and earlier there is a GCA.
>
> It looks like we're currently unconditionally writing the L2C clear
> registers. We should really only be doing this on 3.2 and earlier.

OK, I've pushed the timeline name and tracing to drm-misc-next, and I'll
resend the rest with more comments and the L2C change and outside-in
invalidation once I'm far enough into this CTS run that I'm confident.

Patch
diff mbox series

diff --git a/include/uapi/drm/v3d_drm.h b/include/uapi/drm/v3d_drm.h
index 35c7d813c66e..95b8f8e82ea5 100644
--- a/include/uapi/drm/v3d_drm.h
+++ b/include/uapi/drm/v3d_drm.h
@@ -52,6 +52,13 @@  extern "C" {
  *
  * This asks the kernel to have the GPU execute an optional binner
  * command list, and a render command list.
+ *
+ * The caches (L1T, slice, and L2T) will be flushed before the job
+ * executes.  The TLB writes are guaranteed to have been flushed by
+ * the time the render done IRQ happens, which is the trigger for
+ * out_sync.  Any dirtying of cachelines by the job (only possible
+ * using TMU writes) must be flushed by the caller using the CL's
+ * cache flush commands.
  */
 struct drm_v3d_submit_cl {
 	/* Pointer to the binner command list.