| Message ID | 20181204092548.3038-14-josephl@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Tegra210 DFLL support | expand |
On 04/12/2018 09:25, Joseph Lo wrote: > Add essential DFLL clock properties for Tegra210. > > Signed-off-by: Joseph Lo <josephl@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi > index 2205d66b0443..a6db62157442 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi > @@ -4,6 +4,7 @@ > #include <dt-bindings/memory/tegra210-mc.h> > #include <dt-bindings/pinctrl/pinctrl-tegra.h> > #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> > +#include <dt-bindings/reset/tegra210-car.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/thermal/tegra124-soctherm.h> > > @@ -1131,6 +1132,24 @@ > #nvidia,mipi-calibrate-cells = <1>; > }; > > + dfll: clock@70110000 { > + compatible = "nvidia,tegra210-dfll"; > + reg = <0 0x70110000 0 0x100>, /* DFLL control */ > + <0 0x70110000 0 0x100>, /* I2C output control */ > + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ > + <0 0x70110200 0 0x100>; /* Look-up table RAM */ > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, > + <&tegra_car TEGRA210_CLK_DFLL_REF>, > + <&tegra_car TEGRA210_CLK_I2C5>; > + clock-names = "soc", "ref", "i2c"; > + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; > + reset-names = "dvco"; > + #clock-cells = <0>; > + clock-output-names = "dfllCPU_out"; > + status = "disabled"; > + }; > + > aconnect@702c0000 { > compatible = "nvidia,tegra210-aconnect"; > clocks = <&tegra_car TEGRA210_CLK_APE>, > Acked-by: Jon Hunter <jonathanh@nvidia.com> Cheers Jon
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2205d66b0443..a6db62157442 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/memory/tegra210-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> +#include <dt-bindings/reset/tegra210-car.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/tegra124-soctherm.h> @@ -1131,6 +1132,24 @@ #nvidia,mipi-calibrate-cells = <1>; }; + dfll: clock@70110000 { + compatible = "nvidia,tegra210-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA210_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + status = "disabled"; + }; + aconnect@702c0000 { compatible = "nvidia,tegra210-aconnect"; clocks = <&tegra_car TEGRA210_CLK_APE>,
Add essential DFLL clock properties for Tegra210. Signed-off-by: Joseph Lo <josephl@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)