[v3,12/12] clk: mediatek: Allow changing PLL rate when it is off

Commit Message

Weiyi Lu Dec. 10, 2018, 7:32 a.m. UTC

From: James Liao <[e-mail]>

Some modules may need to change its clock rate before turn on it.
So changing PLL's rate when it is off should be allowed.
This patch removes PLL enabled check before set rate, so that
PLLs can set new frequency even if they are off.

On MT8173 for example, ARMPLL's enable bit can be controlled by
other HW. That means ARMPLL may be turned on even if we (CPU / SW)
set ARMPLL's enable bit as 0. In this case, SW may want and can
still change ARMPLL's rate by changing its pcw and postdiv settings.
But without this patch, new pcw setting will not be applied because
its enable bit is 0.

(am from https://patchwork.kernel.org/patch/9411983/)

Signed-off-by: James Liao <[e-mail]>
Acked-by: Michael Turquette <[e-mail]>
Signed-off-by: Weiyi Lu <[e-mail]>
---
 drivers/clk/mediatek/clk-pll.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

Comments

Stephen Boyd Dec. 14, 2018, 10:01 p.m. UTC | #1

Quoting Weiyi Lu (2018-12-09 23:32:40)
> From: James Liao <[e-mail]>
> 
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are off.
> 
> On MT8173 for example, ARMPLL's enable bit can be controlled by
> other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> set ARMPLL's enable bit as 0. In this case, SW may want and can
> still change ARMPLL's rate by changing its pcw and postdiv settings.
> But without this patch, new pcw setting will not be applied because
> its enable bit is 0.
> 
> (am from https://patchwork.kernel.org/patch/9411983/)

Remove this.

> 
> Signed-off-by: James Liao <[e-mail]>
> Acked-by: Michael Turquette <[e-mail]>
> Signed-off-by: Weiyi Lu <[e-mail]>

Weiyi Lu Feb. 1, 2019, 8:22 a.m. UTC | #2

On Fri, 2018-12-14 at 14:01 -0800, Stephen Boyd wrote:
> Quoting Weiyi Lu (2018-12-09 23:32:40)
> > From: James Liao <[e-mail]>
> > 
> > Some modules may need to change its clock rate before turn on it.
> > So changing PLL's rate when it is off should be allowed.
> > This patch removes PLL enabled check before set rate, so that
> > PLLs can set new frequency even if they are off.
> > 
> > On MT8173 for example, ARMPLL's enable bit can be controlled by
> > other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> > set ARMPLL's enable bit as 0. In this case, SW may want and can
> > still change ARMPLL's rate by changing its pcw and postdiv settings.
> > But without this patch, new pcw setting will not be applied because
> > its enable bit is 0.
> > 
> > (am from https://patchwork.kernel.org/patch/9411983/)
> 
> Remove this.
> 

OK, I'll remove it.

> > 
> > Signed-off-by: James Liao <[e-mail]>
> > Acked-by: Michael Turquette <[e-mail]>
> > Signed-off-by: Weiyi Lu <[e-mail]>

Patch

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 81400601f107..03b20e3bca4e 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -96,13 +96,10 @@  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 		int postdiv)
 {
 	u32 con1, val;
-	int pll_en;
 	u32 tuner_en = 0;
 	u32 tuner_en_mask;
 	void __iomem *tuner_en_addr = NULL;
 
-	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
-
 	/* disable tuner */
 	if (pll->tuner_en_addr) {
 		tuner_en_addr = pll->tuner_en_addr;
@@ -141,8 +138,7 @@  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 
 	con1 = readl(pll->base_addr + REG_CON1);
 
-	if (pll_en)
-		con1 |= CON1_PCW_CHG;
+	con1 |= CON1_PCW_CHG;
 
 	writel(con1, pll->base_addr + REG_CON1);
 	if (pll->tuner_addr)
@@ -155,8 +151,7 @@  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 		writel(val, tuner_en_addr);
 	}
 
-	if (pll_en)
-		udelay(20);
+	udelay(20);
 }
 
 /*