[v2] mmc: sdhci: usdhc: do not do tuning for DDR50 mode.
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Message ID 1545384496-18917-1-git-send-email-haibo.chen@nxp.com
State New
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Series
  • [v2] mmc: sdhci: usdhc: do not do tuning for DDR50 mode.
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Commit Message

BOUGH CHEN Dec. 21, 2018, 9:20 a.m. UTC
DDR50 tuning is optinally defined in sd 3.0 spec. And i.MX
uSDHC internally already uses a fixed optimized timing for
DDR50, normally does not require tuning for DDR50 mode.

This patch specify a new execute_tuning function for i.MX
uSDHC, do not impact i.MX eSDHC.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Adrian Hunter Dec. 21, 2018, 1:50 p.m. UTC | #1
On 21/12/18 11:20 AM, BOUGH CHEN wrote:
> DDR50 tuning is optinally defined in sd 3.0 spec. And i.MX
> uSDHC internally already uses a fixed optimized timing for
> DDR50, normally does not require tuning for DDR50 mode.
> 
> This patch specify a new execute_tuning function for i.MX
> uSDHC, do not impact i.MX eSDHC.
> 
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 75a2484..748ac4e 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -818,6 +818,20 @@ static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
>  			SDHCI_HOST_CONTROL);
>  }
>  
> +static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +
> +	/*
> +	 * i.MX uSDHC internally already uses a fixed optimized timing for
> +	 * DDR50, normally does not require tuning for DDR50 mode.
> +	 */
> +	if (host->timing == MMC_TIMING_UHS_DDR50)
> +		return 0;
> +
> +	return sdhci_execute_tuning(mmc, opcode);
> +}
> +
>  static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
>  {
>  	u32 reg;
> @@ -1338,6 +1352,12 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
>  		writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
>  		writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
>  		writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
> +
> +		/*
> +		 * Link usdhc specific mmc_host_ops execute_tuning function,
> +		 * to replace the standard one in sdhci_ops.
> +		 */
> +		host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
>  	}
>  
>  	if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
>
Ulf Hansson Jan. 14, 2019, 11:42 a.m. UTC | #2
On Fri, 21 Dec 2018 at 10:20, BOUGH CHEN <haibo.chen@nxp.com> wrote:
>
> DDR50 tuning is optinally defined in sd 3.0 spec. And i.MX
> uSDHC internally already uses a fixed optimized timing for
> DDR50, normally does not require tuning for DDR50 mode.
>
> This patch specify a new execute_tuning function for i.MX
> uSDHC, do not impact i.MX eSDHC.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Applied for next, thanks!

Kind regards
Uffe


> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 75a2484..748ac4e 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -818,6 +818,20 @@ static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
>                         SDHCI_HOST_CONTROL);
>  }
>
> +static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
> +{
> +       struct sdhci_host *host = mmc_priv(mmc);
> +
> +       /*
> +        * i.MX uSDHC internally already uses a fixed optimized timing for
> +        * DDR50, normally does not require tuning for DDR50 mode.
> +        */
> +       if (host->timing == MMC_TIMING_UHS_DDR50)
> +               return 0;
> +
> +       return sdhci_execute_tuning(mmc, opcode);
> +}
> +
>  static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
>  {
>         u32 reg;
> @@ -1338,6 +1352,12 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
>                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
>                 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
>                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
> +
> +               /*
> +                * Link usdhc specific mmc_host_ops execute_tuning function,
> +                * to replace the standard one in sdhci_ops.
> +                */
> +               host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
>         }
>
>         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
> --
> 1.9.1
>

Patch
diff mbox series

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 75a2484..748ac4e 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -818,6 +818,20 @@  static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 			SDHCI_HOST_CONTROL);
 }
 
+static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+
+	/*
+	 * i.MX uSDHC internally already uses a fixed optimized timing for
+	 * DDR50, normally does not require tuning for DDR50 mode.
+	 */
+	if (host->timing == MMC_TIMING_UHS_DDR50)
+		return 0;
+
+	return sdhci_execute_tuning(mmc, opcode);
+}
+
 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 {
 	u32 reg;
@@ -1338,6 +1352,12 @@  static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 		writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
 		writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 		writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
+
+		/*
+		 * Link usdhc specific mmc_host_ops execute_tuning function,
+		 * to replace the standard one in sdhci_ops.
+		 */
+		host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
 	}
 
 	if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)