@@ -226,7 +226,7 @@ _i915_param_create_file(struct dentry *parent, const char *name,
static int i915_debugfs_params(struct drm_i915_private *dev_priv)
{
struct drm_minor *minor = dev_priv->drm.primary;
- struct i915_params *params = &i915_modparams;
+ struct i915_params *params = &dev_priv->params;
struct dentry *dir;
dir = debugfs_create_dir("i915_params", minor->debugfs_root);
@@ -261,7 +261,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
intel_driver_caps_print(&dev_priv->caps, &p);
kernel_param_lock(THIS_MODULE);
- i915_params_dump(&i915_modparams, &p);
+ i915_params_dump(&dev_priv->params, &p);
kernel_param_unlock(THIS_MODULE);
return 0;
@@ -1541,7 +1541,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
seq_puts(m, "struct_mutex blocked for reset\n");
- if (!i915_modparams.enable_hangcheck) {
+ if (!dev_priv->params.enable_hangcheck) {
seq_puts(m, "Hangcheck disabled\n");
return 0;
}
@@ -1947,7 +1947,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
intel_runtime_pm_get(dev_priv);
seq_printf(m, "Enabled by kernel parameter: %s\n",
- yesno(i915_modparams.enable_ips));
+ yesno(dev_priv->params.enable_ips));
if (INTEL_GEN(dev_priv) >= 8) {
seq_puts(m, "Currently: unknown\n");
@@ -343,7 +343,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -ENODEV;
break;
case I915_PARAM_HAS_GPU_RESET:
- value = i915_modparams.enable_hangcheck &&
+ value = dev_priv->params.enable_hangcheck &&
intel_has_gpu_reset(dev_priv);
if (value && intel_has_reset_engine(dev_priv))
value = 2;
@@ -1642,6 +1642,9 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
return ERR_PTR(err);
}
+ /* Device parameters start as a copy of module parameters. */
+ i915_params_copy(&i915->params, &i915_modparams);
+
i915->drm.pdev = pdev;
i915->drm.dev_private = i915;
pci_set_drvdata(pdev, &i915->drm);
@@ -1663,6 +1666,9 @@ static void i915_driver_destroy(struct drm_i915_private *i915)
struct pci_dev *pdev = i915->drm.pdev;
drm_dev_fini(&i915->drm);
+
+ i915_params_free(&i915->params);
+
kfree(i915);
/* And make sure we never chase our dangling pointer from pci_dev */
@@ -1692,7 +1698,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
return PTR_ERR(dev_priv);
/* Disable nuclear pageflip by default on pre-ILK */
- if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
+ if (!dev_priv->params.nuclear_pageflip && match_info->gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
ret = pci_enable_device(pdev);
@@ -2222,7 +2228,7 @@ void i915_reset(struct drm_i915_private *i915,
}
if (!intel_has_gpu_reset(i915)) {
- if (i915_modparams.reset)
+ if (i915->params.reset)
dev_err(i915->drm.dev, "GPU reset not supported\n");
else
DRM_DEBUG_DRIVER("GPU reset disabled\n");
@@ -1416,6 +1416,9 @@ struct drm_i915_private {
struct kmem_cache *dependencies;
struct kmem_cache *priorities;
+ /* i915 device parameters */
+ struct i915_params params;
+
const struct intel_device_info info;
struct intel_driver_caps caps;
@@ -2616,7 +2619,7 @@ static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
unsigned long delay;
- if (unlikely(!i915_modparams.enable_hangcheck))
+ if (unlikely(!dev_priv->params.enable_hangcheck))
return;
/* Don't continually defer the hangcheck so that it is always run at
@@ -1650,7 +1650,7 @@ static int eb_prefault_relocations(const struct i915_execbuffer *eb)
const unsigned int count = eb->buffer_count;
unsigned int i;
- if (unlikely(i915_modparams.prefault_disable))
+ if (unlikely(eb->i915->params.prefault_disable))
return 0;
for (i = 0; i < count; i++) {
@@ -1829,7 +1829,7 @@ static void capture_gen_state(struct i915_gpu_state *error)
static void capture_params(struct i915_gpu_state *error)
{
- i915_params_copy(&error->params, &i915_modparams);
+ i915_params_copy(&error->params, &error->i915->params);
}
static unsigned long capture_find_epoch(const struct i915_gpu_state *error)
@@ -1929,7 +1929,7 @@ void i915_capture_error_state(struct drm_i915_private *i915,
struct i915_gpu_state *error;
unsigned long flags;
- if (!i915_modparams.error_capture)
+ if (!i915->params.error_capture)
return;
if (READ_ONCE(i915->gpu_error.first_error))
@@ -354,7 +354,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
struct drm_display_mode *panel_fixed_mode;
int index;
- index = i915_modparams.vbt_sdvo_panel_type;
+ index = dev_priv->params.vbt_sdvo_panel_type;
if (index == -2) {
DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
return;
@@ -662,9 +662,9 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
u8 vswing;
/* Don't read from VBT if module parameter has valid value*/
- if (i915_modparams.edp_vswing) {
+ if (dev_priv->params.edp_vswing) {
dev_priv->vbt.edp.low_vswing =
- i915_modparams.edp_vswing == 1;
+ dev_priv->params.edp_vswing == 1;
} else {
vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
dev_priv->vbt.edp.low_vswing = vswing == 0;
@@ -784,7 +784,7 @@ intel_crt_detect(struct drm_connector *connector,
connector->base.id, connector->name,
force);
- if (i915_modparams.load_detect_test) {
+ if (dev_priv->params.load_detect_test) {
intel_display_power_get(dev_priv, intel_encoder->power_domain);
goto load_detect;
}
@@ -836,7 +836,7 @@ intel_crt_detect(struct drm_connector *connector,
else if (INTEL_GEN(dev_priv) < 4)
status = intel_crt_load_detect(crt,
to_intel_crtc(connector->state->crtc)->pipe);
- else if (i915_modparams.load_detect_test)
+ else if (dev_priv->params.load_detect_test)
status = connector_status_disconnected;
else
status = connector_status_unknown;
@@ -498,14 +498,14 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
}
- if (i915_modparams.dmc_firmware_path) {
- if (strlen(i915_modparams.dmc_firmware_path) == 0) {
+ if (dev_priv->params.dmc_firmware_path) {
+ if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
csr->fw_path = NULL;
DRM_INFO("Disabling CSR firmware and runtime PM\n");
return;
}
- csr->fw_path = i915_modparams.dmc_firmware_path;
+ csr->fw_path = dev_priv->params.dmc_firmware_path;
/* Bypass version check for firmware override. */
csr->required_version = 0;
}
@@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
info->num_sprites[pipe] = 1;
}
- if (i915_modparams.disable_display) {
+ if (dev_priv->params.disable_display) {
DRM_INFO("Display disabled (module parameter)\n");
info->num_pipes = 0;
} else if (HAS_DISPLAY(dev_priv) &&
@@ -3758,7 +3758,7 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv)
int ret;
/* reset doesn't touch the display */
- if (!i915_modparams.force_reset_modeset_test &&
+ if (!dev_priv->params.force_reset_modeset_test &&
!gpu_reset_clobbers_display(dev_priv))
return;
@@ -6546,7 +6546,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
if (!hsw_crtc_supports_ips(crtc))
return false;
- if (!i915_modparams.enable_ips)
+ if (!dev_priv->params.enable_ips)
return false;
if (crtc_state->pipe_bpp > 24)
@@ -6773,8 +6773,8 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
{
- if (i915_modparams.panel_use_ssc >= 0)
- return i915_modparams.panel_use_ssc != 0;
+ if (dev_priv->params.panel_use_ssc >= 0)
+ return dev_priv->params.panel_use_ssc != 0;
return dev_priv->vbt.lvds_use_ssc
&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
}
@@ -12674,7 +12674,7 @@ static int intel_atomic_check(struct drm_device *dev,
return ret;
}
- if (i915_modparams.fastboot &&
+ if (dev_priv->params.fastboot &&
intel_pipe_config_compare(dev_priv,
to_intel_crtc_state(old_crtc_state),
pipe_config, true)) {
@@ -4235,7 +4235,10 @@ intel_dp_sink_can_mst(struct intel_dp *intel_dp)
static bool
intel_dp_can_mst(struct intel_dp *intel_dp)
{
- return i915_modparams.enable_dp_mst &&
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+
+ return dev_priv->params.enable_dp_mst &&
intel_dp->can_mst &&
intel_dp_sink_can_mst(intel_dp);
}
@@ -4243,19 +4246,21 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
static void
intel_dp_configure_mst(struct intel_dp *intel_dp)
{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
struct intel_encoder *encoder =
&dp_to_dig_port(intel_dp)->base;
bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
port_name(encoder->port), yesno(intel_dp->can_mst),
- yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
+ yesno(sink_can_mst), yesno(dev_priv->params.enable_dp_mst));
if (!intel_dp->can_mst)
return;
intel_dp->is_mst = sink_can_mst &&
- i915_modparams.enable_dp_mst;
+ dev_priv->params.enable_dp_mst;
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
intel_dp->is_mst);
@@ -262,9 +262,10 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector)
int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
{
+ struct drm_i915_private *dev_priv = to_i915(intel_connector->base.dev);
struct intel_panel *panel = &intel_connector->panel;
- if (!i915_modparams.enable_dpcd_backlight)
+ if (!dev_priv->params.enable_dpcd_backlight)
return -ENODEV;
if (!intel_dp_aux_display_control_capable(intel_connector))
@@ -805,7 +805,7 @@ static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
return false;
}
- if (!i915_modparams.enable_fbc) {
+ if (!dev_priv->params.enable_fbc) {
fbc->no_fbc_reason = "disabled per module param or by default";
return false;
}
@@ -914,7 +914,7 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc)
fbc->flip_pending = false;
WARN_ON(fbc->active);
- if (!i915_modparams.enable_fbc) {
+ if (!dev_priv->params.enable_fbc) {
intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
__intel_fbc_disable(dev_priv);
@@ -1272,8 +1272,8 @@ void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
*/
static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
{
- if (i915_modparams.enable_fbc >= 0)
- return !!i915_modparams.enable_fbc;
+ if (dev_priv->params.enable_fbc >= 0)
+ return !!dev_priv->params.enable_fbc;
if (!HAS_FBC(dev_priv))
return 0;
@@ -1314,9 +1314,9 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
if (need_fbc_vtd_wa(dev_priv))
mkwrite_device_info(dev_priv)->display.has_fbc = false;
- i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
+ dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv);
DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
- i915_modparams.enable_fbc);
+ dev_priv->params.enable_fbc);
if (!HAS_FBC(dev_priv)) {
fbc->no_fbc_reason = "unsupported by this chipset";
@@ -61,8 +61,8 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
if (!HAS_GUC(dev_priv))
return;
- if (i915_modparams.guc_firmware_path) {
- guc_fw->path = i915_modparams.guc_firmware_path;
+ if (dev_priv->params.guc_firmware_path) {
+ guc_fw->path = dev_priv->params.guc_firmware_path;
guc_fw->major_ver_wanted = 0;
guc_fw->minor_ver_wanted = 0;
} else if (IS_SKYLAKE(dev_priv)) {
@@ -451,6 +451,7 @@ static void guc_log_capture_logs(struct intel_guc_log *log)
int intel_guc_log_create(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct i915_vma *vma;
u32 guc_log_size;
int ret;
@@ -487,7 +488,7 @@ int intel_guc_log_create(struct intel_guc_log *log)
log->vma = vma;
- log->level = i915_modparams.guc_log_level;
+ log->level = dev_priv->params.guc_log_level;
return 0;
@@ -60,7 +60,7 @@ static bool is_supported_device(struct drm_i915_private *dev_priv)
*/
void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
{
- if (!i915_modparams.enable_gvt)
+ if (!dev_priv->params.enable_gvt)
return;
if (intel_vgpu_active(dev_priv)) {
@@ -75,7 +75,7 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
return;
bail:
- i915_modparams.enable_gvt = 0;
+ dev_priv->params.enable_gvt = 0;
}
/**
@@ -95,7 +95,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
if (i915_inject_load_failure())
return -ENODEV;
- if (!i915_modparams.enable_gvt) {
+ if (!dev_priv->params.enable_gvt) {
DRM_DEBUG_DRIVER("GVT-g is disabled by kernel params\n");
return 0;
}
@@ -123,7 +123,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return 0;
bail:
- i915_modparams.enable_gvt = 0;
+ dev_priv->params.enable_gvt = 0;
return 0;
}
@@ -415,7 +415,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
enum intel_engine_id id;
unsigned int hung = 0, stuck = 0, wedged = 0;
- if (!i915_modparams.enable_hangcheck)
+ if (!dev_priv->params.enable_hangcheck)
return;
if (!READ_ONCE(dev_priv->gt.awake))
@@ -60,8 +60,8 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
if (!HAS_HUC(dev_priv))
return;
- if (i915_modparams.huc_firmware_path) {
- huc_fw->path = i915_modparams.huc_firmware_path;
+ if (dev_priv->params.huc_firmware_path) {
+ huc_fw->path = dev_priv->params.huc_firmware_path;
huc_fw->major_ver_wanted = 0;
huc_fw->minor_ver_wanted = 0;
} else if (IS_SKYLAKE(dev_priv)) {
@@ -770,8 +770,8 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
struct drm_i915_private *dev_priv = to_i915(dev);
/* use the module option value if specified */
- if (i915_modparams.lvds_channel_mode > 0)
- return i915_modparams.lvds_channel_mode == 2;
+ if (dev_priv->params.lvds_channel_mode > 0)
+ return dev_priv->params.lvds_channel_mode == 2;
/* single channel LVDS is limited to 112 MHz */
if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999)
@@ -852,7 +852,7 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv)
{
struct intel_opregion *opregion = &dev_priv->opregion;
const struct firmware *fw = NULL;
- const char *name = i915_modparams.vbt_firmware;
+ const char *name = dev_priv->params.vbt_firmware;
int ret;
if (!name || !*name)
@@ -449,10 +449,10 @@ static u32 intel_panel_compute_brightness(struct intel_connector *connector,
WARN_ON(panel->backlight.max == 0);
- if (i915_modparams.invert_brightness < 0)
+ if (dev_priv->params.invert_brightness < 0)
return val;
- if (i915_modparams.invert_brightness > 0 ||
+ if (dev_priv->params.invert_brightness > 0 ||
dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
return panel->backlight.max - val + panel->backlight.min;
}
@@ -56,11 +56,11 @@
#include "intel_drv.h"
#include "i915_drv.h"
-static bool psr_global_enabled(u32 debug)
+static bool psr_global_enabled(struct drm_i915_private *dev_priv, u32 debug)
{
switch (debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_DEFAULT:
- return i915_modparams.enable_psr;
+ return dev_priv->params.enable_psr;
case I915_PSR_DEBUG_DISABLE:
return false;
default:
@@ -72,7 +72,7 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state)
{
/* Disable PSR2 by default for all platforms */
- if (i915_modparams.enable_psr == -1)
+ if (dev_priv->params.enable_psr == -1)
return false;
/* Cannot enable DSC and PSR2 simultaneously */
@@ -763,7 +763,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
dev_priv->psr.prepared = true;
dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
- if (psr_global_enabled(dev_priv->psr.debug))
+ if (psr_global_enabled(dev_priv, dev_priv->psr.debug))
intel_psr_enable_locked(dev_priv, crtc_state);
else
DRM_DEBUG_KMS("PSR disabled by flag\n");
@@ -990,7 +990,7 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
if (ret)
return ret;
- enable = psr_global_enabled(val);
+ enable = psr_global_enabled(dev_priv, val);
if (!enable || switching_psr(dev_priv, crtc_state, mode))
intel_psr_disable_locked(dev_priv->psr.dp);
@@ -1160,9 +1160,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
if (!dev_priv->psr.sink_support)
return;
- if (i915_modparams.enable_psr == -1)
+ if (dev_priv->params.enable_psr == -1)
if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
- i915_modparams.enable_psr = 0;
+ dev_priv->params.enable_psr = 0;
/*
* If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
@@ -3069,7 +3069,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
mask = 0;
}
- if (!i915_modparams.disable_power_well)
+ if (!dev_priv->params.disable_power_well)
max_dc = 0;
if (enable_dc >= 0 && enable_dc <= max_dc) {
@@ -3143,11 +3143,11 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
struct i915_power_domains *power_domains = &dev_priv->power_domains;
int err;
- i915_modparams.disable_power_well =
+ dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
- i915_modparams.disable_power_well);
+ dev_priv->params.disable_power_well);
dev_priv->csr.allowed_dc_mask =
- get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc);
+ get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
@@ -3759,7 +3759,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
*/
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
/* Disable power support if the user asked so. */
- if (!i915_modparams.disable_power_well)
+ if (!dev_priv->params.disable_power_well)
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
intel_power_domains_sync_hw(dev_priv);
@@ -3783,7 +3783,7 @@ void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv)
intel_runtime_pm_put(dev_priv);
/* Remove the refcount we took to keep power well support disabled. */
- if (!i915_modparams.disable_power_well)
+ if (!dev_priv->params.disable_power_well)
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
intel_power_domains_verify_state(dev_priv);
@@ -3858,7 +3858,7 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
* Even if power well support was disabled we still want to disable
* power wells if power domains must be deinitialized for suspend.
*/
- if (!i915_modparams.disable_power_well) {
+ if (!dev_priv->params.disable_power_well) {
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
intel_power_domains_verify_state(dev_priv);
}
@@ -107,18 +107,18 @@ static void sanitize_options_early(struct drm_i915_private *i915)
struct intel_uc_fw *huc_fw = &i915->huc.fw;
/* A negative value means "use platform default" */
- if (i915_modparams.enable_guc < 0)
- i915_modparams.enable_guc = __get_platform_enable_guc(i915);
+ if (i915->params.enable_guc < 0)
+ i915->params.enable_guc = __get_platform_enable_guc(i915);
DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
- i915_modparams.enable_guc,
+ i915->params.enable_guc,
yesno(intel_uc_is_using_guc_submission(i915)),
yesno(intel_uc_is_using_huc(i915)));
/* Verify GuC firmware availability */
if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
- "enable_guc", i915_modparams.enable_guc,
+ "enable_guc", i915->params.enable_guc,
!HAS_GUC(i915) ? "no GuC hardware" :
"no GuC firmware");
}
@@ -126,40 +126,40 @@ static void sanitize_options_early(struct drm_i915_private *i915)
/* Verify HuC firmware availability */
if (intel_uc_is_using_huc(i915) && !intel_uc_fw_is_selected(huc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
- "enable_guc", i915_modparams.enable_guc,
+ "enable_guc", i915->params.enable_guc,
!HAS_HUC(i915) ? "no HuC hardware" :
"no HuC firmware");
}
/* A negative value means "use platform/config default" */
- if (i915_modparams.guc_log_level < 0)
- i915_modparams.guc_log_level =
+ if (i915->params.guc_log_level < 0)
+ i915->params.guc_log_level =
__get_default_guc_log_level(i915);
- if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
+ if (i915->params.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
- "guc_log_level", i915_modparams.guc_log_level,
+ "guc_log_level", i915->params.guc_log_level,
!HAS_GUC(i915) ? "no GuC hardware" :
"GuC not enabled");
- i915_modparams.guc_log_level = 0;
+ i915->params.guc_log_level = 0;
}
- if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
+ if (i915->params.guc_log_level > GUC_LOG_LEVEL_MAX) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
- "guc_log_level", i915_modparams.guc_log_level,
+ "guc_log_level", i915->params.guc_log_level,
"verbosity too high");
- i915_modparams.guc_log_level = GUC_LOG_LEVEL_MAX;
+ i915->params.guc_log_level = GUC_LOG_LEVEL_MAX;
}
DRM_DEBUG_DRIVER("guc_log_level=%d (enabled:%s, verbose:%s, verbosity:%d)\n",
- i915_modparams.guc_log_level,
- yesno(i915_modparams.guc_log_level),
- yesno(GUC_LOG_LEVEL_IS_VERBOSE(i915_modparams.guc_log_level)),
- GUC_LOG_LEVEL_TO_VERBOSITY(i915_modparams.guc_log_level));
+ i915->params.guc_log_level,
+ yesno(i915->params.guc_log_level),
+ yesno(GUC_LOG_LEVEL_IS_VERBOSE(i915->params.guc_log_level)),
+ GUC_LOG_LEVEL_TO_VERBOSITY(i915->params.guc_log_level));
/* Make sure that sanitization was done */
- GEM_BUG_ON(i915_modparams.enable_guc < 0);
- GEM_BUG_ON(i915_modparams.guc_log_level < 0);
+ GEM_BUG_ON(i915->params.enable_guc < 0);
+ GEM_BUG_ON(i915->params.guc_log_level < 0);
}
void intel_uc_init_early(struct drm_i915_private *i915)
@@ -493,3 +493,21 @@ int intel_uc_resume(struct drm_i915_private *i915)
return 0;
}
+
+bool intel_uc_is_using_guc(struct drm_i915_private *dev_priv)
+{
+ GEM_BUG_ON(dev_priv->params.enable_guc < 0);
+ return dev_priv->params.enable_guc > 0;
+}
+
+bool intel_uc_is_using_guc_submission(struct drm_i915_private *dev_priv)
+{
+ GEM_BUG_ON(dev_priv->params.enable_guc < 0);
+ return dev_priv->params.enable_guc & ENABLE_GUC_SUBMISSION;
+}
+
+bool intel_uc_is_using_huc(struct drm_i915_private *dev_priv)
+{
+ GEM_BUG_ON(dev_priv->params.enable_guc < 0);
+ return dev_priv->params.enable_guc & ENABLE_GUC_LOAD_HUC;
+}
@@ -26,7 +26,6 @@
#include "intel_guc.h"
#include "intel_huc.h"
-#include "i915_params.h"
void intel_uc_init_early(struct drm_i915_private *dev_priv);
void intel_uc_cleanup_early(struct drm_i915_private *dev_priv);
@@ -41,22 +40,8 @@ void intel_uc_fini(struct drm_i915_private *dev_priv);
int intel_uc_suspend(struct drm_i915_private *dev_priv);
int intel_uc_resume(struct drm_i915_private *dev_priv);
-static inline bool intel_uc_is_using_guc(struct drm_i915_private *dev_priv)
-{
- GEM_BUG_ON(i915_modparams.enable_guc < 0);
- return i915_modparams.enable_guc > 0;
-}
-
-static inline bool intel_uc_is_using_guc_submission(struct drm_i915_private *dev_priv)
-{
- GEM_BUG_ON(i915_modparams.enable_guc < 0);
- return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION;
-}
-
-static inline bool intel_uc_is_using_huc(struct drm_i915_private *dev_priv)
-{
- GEM_BUG_ON(i915_modparams.enable_guc < 0);
- return i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC;
-}
+bool intel_uc_is_using_guc(struct drm_i915_private *dev_priv);
+bool intel_uc_is_using_guc_submission(struct drm_i915_private *dev_priv);
+bool intel_uc_is_using_huc(struct drm_i915_private *dev_priv);
#endif
@@ -663,10 +663,10 @@ void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
dev_priv->uncore.user_forcewake.saved_mmio_check =
dev_priv->uncore.unclaimed_mmio_check;
dev_priv->uncore.user_forcewake.saved_mmio_debug =
- i915_modparams.mmio_debug;
+ dev_priv->params.mmio_debug;
dev_priv->uncore.unclaimed_mmio_check = 0;
- i915_modparams.mmio_debug = 0;
+ dev_priv->params.mmio_debug = 0;
}
spin_unlock_irq(&dev_priv->uncore.lock);
}
@@ -688,7 +688,7 @@ void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
dev_priv->uncore.unclaimed_mmio_check =
dev_priv->uncore.user_forcewake.saved_mmio_check;
- i915_modparams.mmio_debug =
+ dev_priv->params.mmio_debug =
dev_priv->uncore.user_forcewake.saved_mmio_debug;
intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
@@ -1092,7 +1092,7 @@ __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
read ? "read from" : "write to",
i915_mmio_reg_offset(reg)))
/* Only report the first N failures */
- i915_modparams.mmio_debug--;
+ dev_priv->params.mmio_debug--;
}
static inline void
@@ -1101,7 +1101,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
const bool read,
const bool before)
{
- if (likely(!i915_modparams.mmio_debug))
+ if (likely(!dev_priv->params.mmio_debug))
return;
__unclaimed_reg_debug(dev_priv, reg, read, before);
@@ -2271,7 +2271,7 @@ typedef int (*reset_func)(struct drm_i915_private *,
static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
{
- if (!i915_modparams.reset)
+ if (!dev_priv->params.reset)
return NULL;
if (INTEL_GEN(dev_priv) >= 8)
@@ -2362,7 +2362,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
{
return (dev_priv->info.has_reset_engine &&
- i915_modparams.reset >= 2);
+ dev_priv->params.reset >= 2);
}
int intel_reset_guc(struct drm_i915_private *dev_priv)
@@ -2396,11 +2396,11 @@ intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
goto out;
if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
- if (!i915_modparams.mmio_debug) {
+ if (!dev_priv->params.mmio_debug) {
DRM_DEBUG("Unclaimed register detected, "
"enabling oneshot unclaimed register reporting. "
"Please use i915.mmio_debug=N for more information.\n");
- i915_modparams.mmio_debug++;
+ dev_priv->params.mmio_debug++;
}
dev_priv->uncore.unclaimed_mmio_check--;
ret = true;
@@ -1670,7 +1670,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
return -EIO; /* we're long past hope of a successful reset */
intel_runtime_pm_get(i915);
- saved_hangcheck = fetch_and_zero(&i915_modparams.enable_hangcheck);
+ saved_hangcheck = fetch_and_zero(&i915->params.enable_hangcheck);
err = i915_subtests(tests, i915);
@@ -1678,7 +1678,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
igt_flush_test(i915, I915_WAIT_LOCKED);
mutex_unlock(&i915->drm.struct_mutex);
- i915_modparams.enable_hangcheck = saved_hangcheck;
+ i915->params.enable_hangcheck = saved_hangcheck;
intel_runtime_pm_put(i915);
return err;
Start using device specific parameters instead of module parameters for most things. The module parameters become the immutable initial values for i915 parameters. Any later changes are only reflected in the debugfs. The stragglers are: * i915.alpha_support and i915.modeset. Needed before dev_priv is available. This is fine because the parameters are read-only and never modified. * i915.verbose_state_checks. Passing dev_priv to I915_STATE_WARN and I915_STATE_WARN_ON would result in massive and ugly churn. This is handled by not exposing the parameter via debugfs, and leaving the parameter writable in sysfs. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 8 ++-- drivers/gpu/drm/i915/i915_drv.c | 12 +++-- drivers/gpu/drm/i915/i915_drv.h | 5 ++- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- drivers/gpu/drm/i915/intel_bios.c | 6 +-- drivers/gpu/drm/i915/intel_crt.c | 4 +- drivers/gpu/drm/i915/intel_csr.c | 6 +-- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 10 ++--- drivers/gpu/drm/i915/intel_dp.c | 11 +++-- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 3 +- drivers/gpu/drm/i915/intel_fbc.c | 12 ++--- drivers/gpu/drm/i915/intel_guc_fw.c | 4 +- drivers/gpu/drm/i915/intel_guc_log.c | 3 +- drivers/gpu/drm/i915/intel_gvt.c | 8 ++-- drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- drivers/gpu/drm/i915/intel_huc_fw.c | 4 +- drivers/gpu/drm/i915/intel_lvds.c | 4 +- drivers/gpu/drm/i915/intel_opregion.c | 2 +- drivers/gpu/drm/i915/intel_panel.c | 4 +- drivers/gpu/drm/i915/intel_psr.c | 14 +++--- drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++--- drivers/gpu/drm/i915/intel_uc.c | 56 ++++++++++++++++-------- drivers/gpu/drm/i915/intel_uc.h | 21 ++------- drivers/gpu/drm/i915/intel_uncore.c | 18 ++++---- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 4 +- 27 files changed, 131 insertions(+), 112 deletions(-)