[1/3] media: dt-bindings: media: Fix MTK document for vcodec
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Message ID 1545978785-31375-1-git-send-email-yunfei.dong@mediatek.com
State New
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  • [1/3] media: dt-bindings: media: Fix MTK document for vcodec
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Commit Message

Yunfei Dong Dec. 28, 2018, 6:33 a.m. UTC
Fix MTK binding document for MT8173 dtsi changed in order
to use standard CCF interface.
MT8173 SoC from Mediatek.

Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Signed-off-by: Qianqian Yan <qianqian.yan@mediatek.com>
---
 .../devicetree/bindings/media/mediatek-vcodec.txt   | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Rob Herring Jan. 3, 2019, 11:17 p.m. UTC | #1
On Fri, Dec 28, 2018 at 02:33:03PM +0800, Yunfei Dong wrote:
> Fix MTK binding document for MT8173 dtsi changed in order
> to use standard CCF interface.
> MT8173 SoC from Mediatek.

A better subject would be "add 'assigned-clocks' to vcodec examples".

> 
> Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> Signed-off-by: Qianqian Yan <qianqian.yan@mediatek.com>
> ---
>  .../devicetree/bindings/media/mediatek-vcodec.txt   | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> index 2a615d84a682..b6b5dde6abd8 100644
> --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> @@ -66,6 +66,15 @@ vcodec_dec: vcodec@16000000 {
>                    "vencpll",
>                    "venc_lt_sel",
>                    "vdec_bus_clk_src";
> +    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
> +                      <&topckgen CLK_TOP_CCI400_SEL>,
> +                      <&topckgen CLK_TOP_VDEC_SEL>,
> +                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
> +                      <&apmixedsys CLK_APMIXED_VENCPLL>;
> +    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
> +                             <&topckgen CLK_TOP_UNIVPLL_D2>,
> +                             <&topckgen CLK_TOP_VCODECPLL>;
> +    assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
>    };
>  
>    vcodec_enc: vcodec@18002000 {
> @@ -105,4 +114,8 @@ vcodec_dec: vcodec@16000000 {
>                    "venc_sel",
>                    "venc_lt_sel_src",
>                    "venc_lt_sel";
> +    assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
> +                      <&topckgen CLK_TOP_VENC_LT_SEL>;
> +    assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
> +                             <&topckgen CLK_TOP_UNIVPLL1_D2>;
>    };
> -- 
> 2.19.1
>
Yunfei Dong Jan. 4, 2019, 3:32 a.m. UTC | #2
Hi Rob,

Thanks for your advice, I already sent the second patch.

Change note:
1: modify the subject for 0001*
2: modify the description for 0003

Best Regards,
Yunfei Dong


On Thu, 2019-01-03 at 17:17 -0600, Rob Herring wrote:
> On Fri, Dec 28, 2018 at 02:33:03PM +0800, Yunfei Dong wrote:
> > Fix MTK binding document for MT8173 dtsi changed in order
> > to use standard CCF interface.
> > MT8173 SoC from Mediatek.
> 
> A better subject would be "add 'assigned-clocks' to vcodec examples".
> 
> > 
> > Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> > Signed-off-by: Qianqian Yan <qianqian.yan@mediatek.com>
> > ---
> >  .../devicetree/bindings/media/mediatek-vcodec.txt   | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> > index 2a615d84a682..b6b5dde6abd8 100644
> > --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> > @@ -66,6 +66,15 @@ vcodec_dec: vcodec@16000000 {
> >                    "vencpll",
> >                    "venc_lt_sel",
> >                    "vdec_bus_clk_src";
> > +    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
> > +                      <&topckgen CLK_TOP_CCI400_SEL>,
> > +                      <&topckgen CLK_TOP_VDEC_SEL>,
> > +                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
> > +                      <&apmixedsys CLK_APMIXED_VENCPLL>;
> > +    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
> > +                             <&topckgen CLK_TOP_UNIVPLL_D2>,
> > +                             <&topckgen CLK_TOP_VCODECPLL>;
> > +    assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
> >    };
> >  
> >    vcodec_enc: vcodec@18002000 {
> > @@ -105,4 +114,8 @@ vcodec_dec: vcodec@16000000 {
> >                    "venc_sel",
> >                    "venc_lt_sel_src",
> >                    "venc_lt_sel";
> > +    assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
> > +                      <&topckgen CLK_TOP_VENC_LT_SEL>;
> > +    assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
> > +                             <&topckgen CLK_TOP_UNIVPLL1_D2>;
> >    };
> > -- 
> > 2.19.1
> >

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
index 2a615d84a682..b6b5dde6abd8 100644
--- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
+++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
@@ -66,6 +66,15 @@  vcodec_dec: vcodec@16000000 {
                   "vencpll",
                   "venc_lt_sel",
                   "vdec_bus_clk_src";
+    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
+                      <&topckgen CLK_TOP_CCI400_SEL>,
+                      <&topckgen CLK_TOP_VDEC_SEL>,
+                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
+                      <&apmixedsys CLK_APMIXED_VENCPLL>;
+    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
+                             <&topckgen CLK_TOP_UNIVPLL_D2>,
+                             <&topckgen CLK_TOP_VCODECPLL>;
+    assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
   };
 
   vcodec_enc: vcodec@18002000 {
@@ -105,4 +114,8 @@  vcodec_dec: vcodec@16000000 {
                   "venc_sel",
                   "venc_lt_sel_src",
                   "venc_lt_sel";
+    assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
+                      <&topckgen CLK_TOP_VENC_LT_SEL>;
+    assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
+                             <&topckgen CLK_TOP_UNIVPLL1_D2>;
   };