| Message ID | 1546314952-15990-11-git-send-email-yong.wu@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MT8183 IOMMU SUPPORT | expand |
On Mon, Dec 31, 2018 at 7:58 PM Yong Wu <yong.wu@mediatek.com> wrote: > > In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while > it is extended to REG_MMU_CTRL which contains _STANDARD_AXI_MODE in > the other SoCs. I move this property to plat_data since both mt8173 > and mt8183 use this property. > > It is a preparing patch for mt8183. > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > --- > drivers/iommu/mtk_iommu.c | 4 ++-- > drivers/iommu/mtk_iommu.h | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 35a1263..8d8ab21 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -558,8 +558,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > } > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > - /* It's MISC control register whose default value is ok except mt8173.*/ > - if (data->plat_data->m4u_plat == M4U_MT8173) > + if (data->plat_data->reset_axi) > writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); The commit description makes it sound like the overall format of the register is the same, but the "other SoCs" have some extra bits they'd like to leave alone. Would it be easier to do a read-modify-write to always clear some bits in the register, instead of doing something based on the SoC? Or do the bits mean completely different things in the different versions (in which case what you've got makes sense to me)? -Evan
On Wed, 2019-01-30 at 10:30 -0800, Evan Green wrote: > On Mon, Dec 31, 2018 at 7:58 PM Yong Wu <yong.wu@mediatek.com> wrote: > > > > In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while > > it is extended to REG_MMU_CTRL which contains _STANDARD_AXI_MODE in > > the other SoCs. I move this property to plat_data since both mt8173 > > and mt8183 use this property. > > > > It is a preparing patch for mt8183. > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > > --- > > drivers/iommu/mtk_iommu.c | 4 ++-- > > drivers/iommu/mtk_iommu.h | 2 +- > > 2 files changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 35a1263..8d8ab21 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -558,8 +558,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > > } > > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > > > - /* It's MISC control register whose default value is ok except mt8173.*/ > > - if (data->plat_data->m4u_plat == M4U_MT8173) > > + if (data->plat_data->reset_axi) > > writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); > > The commit description makes it sound like the overall format of the > register is the same, but the "other SoCs" have some extra bits they'd > like to leave alone. Would it be easier to do a read-modify-write to > always clear some bits in the register, instead of doing something > based on the SoC? Or do the bits mean completely different things in > the different versions (in which case what you've got makes sense to > me)? The bits mean completely is different.(the axi bit position also is different. I will add this in the comment of this patch.) > -Evan
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 35a1263..8d8ab21 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -558,8 +558,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); - /* It's MISC control register whose default value is ok except mt8173.*/ - if (data->plat_data->m4u_plat == M4U_MT8173) + if (data->plat_data->reset_axi) writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, @@ -749,6 +748,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) .m4u_plat = M4U_MT8173, .has_4gb_mode = true, .has_bclk = true, + .reset_axi = true, .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ }; diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index eec19a6..b46aeaa 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -47,7 +47,7 @@ struct mtk_iommu_plat_data { /* HW will use the EMI clock if there isn't the "bclk". */ bool has_bclk; - + bool reset_axi; unsigned char larbid_remap[MTK_LARB_NR_MAX]; };
In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while it is extended to REG_MMU_CTRL which contains _STANDARD_AXI_MODE in the other SoCs. I move this property to plat_data since both mt8173 and mt8183 use this property. It is a preparing patch for mt8183. Signed-off-by: Yong Wu <yong.wu@mediatek.com> --- drivers/iommu/mtk_iommu.c | 4 ++-- drivers/iommu/mtk_iommu.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)