| Message ID | 1546314952-15990-15-git-send-email-yong.wu@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MT8183 IOMMU SUPPORT | expand |
On Mon, Dec 31, 2018 at 7:59 PM Yong Wu <yong.wu@mediatek.com> wrote: > > Normally the M4U HW connect EMI with smi. the diagram is like below: > EMI > | > M4U > | > smi-common > | > ----------------- > | | | | ... > larb0 larb1 larb2 larb3 > > Actually there are 2 mmu cells in the M4U HW, like this diagram: > > EMI > --------- > | | > mmu0 mmu1 <- M4U > | | > --------- > | > smi-common > | > ----------------- > | | | | ... > larb0 larb1 larb2 larb3 > > This patch add support for mmu1. In order to get better performance, > we could adjust some larbs go to mmu1 while the others still go to > mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220). > > mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default > value of that register is 0 which means all the larbs go to mmu0 > defaultly. > > This is a preparing patch for adjusting SMI_BUS_SEL for mt8183. > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > --- > drivers/iommu/mtk_iommu.c | 47 +++++++++++++++++++++++++++++------------------ > 1 file changed, 29 insertions(+), 18 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 66e3615..7fcef19 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -70,27 +70,32 @@ > #define F_MISS_FIFO_ERR_INT_EN BIT(6) > #define F_INT_CLR_BIT BIT(12) > > -#define REG_MMU_INT_MAIN_CONTROL 0x124 > -#define F_INT_TRANSLATION_FAULT BIT(0) > -#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) > -#define F_INT_INVALID_PA_FAULT BIT(2) > -#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) > -#define F_INT_TLB_MISS_FAULT BIT(4) > -#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) > -#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) > +#define REG_MMU_INT_MAIN_CONTROL 0x124 /* mmu0 | mmu1 */ The comment being on that line is kind of weird, since the comment really applies to the lines below it. Maybe the comment should be on its own line, or on the TRANSLATION_FAULT line. Other than that, Reviewed-by: Evan Green <evgreen@chromium.org>
On Wed, 2019-01-30 at 10:55 -0800, Evan Green wrote: > On Mon, Dec 31, 2018 at 7:59 PM Yong Wu <yong.wu@mediatek.com> wrote: > > > > Normally the M4U HW connect EMI with smi. the diagram is like below: > > EMI > > | > > M4U > > | > > smi-common > > | > > ----------------- > > | | | | ... > > larb0 larb1 larb2 larb3 > > > > Actually there are 2 mmu cells in the M4U HW, like this diagram: > > > > EMI > > --------- > > | | > > mmu0 mmu1 <- M4U > > | | > > --------- > > | > > smi-common > > | > > ----------------- > > | | | | ... > > larb0 larb1 larb2 larb3 > > > > This patch add support for mmu1. In order to get better performance, > > we could adjust some larbs go to mmu1 while the others still go to > > mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220). > > > > mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default > > value of that register is 0 which means all the larbs go to mmu0 > > defaultly. > > > > This is a preparing patch for adjusting SMI_BUS_SEL for mt8183. > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com> > > --- > > drivers/iommu/mtk_iommu.c | 47 +++++++++++++++++++++++++++++------------------ > > 1 file changed, 29 insertions(+), 18 deletions(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 66e3615..7fcef19 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -70,27 +70,32 @@ > > #define F_MISS_FIFO_ERR_INT_EN BIT(6) > > #define F_INT_CLR_BIT BIT(12) > > > > -#define REG_MMU_INT_MAIN_CONTROL 0x124 > > -#define F_INT_TRANSLATION_FAULT BIT(0) > > -#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) > > -#define F_INT_INVALID_PA_FAULT BIT(2) > > -#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) > > -#define F_INT_TLB_MISS_FAULT BIT(4) > > -#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) > > -#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) > > +#define REG_MMU_INT_MAIN_CONTROL 0x124 /* mmu0 | mmu1 */ > > The comment being on that line is kind of weird, since the comment > really applies to the lines below it. Maybe the comment should be on > its own line, or on the TRANSLATION_FAULT line. Sharp eye. You are right, this comment applies the lines below. But If I move it below, then the next line will be over 80 chars. How about I add a "below:" like this: > +#define REG_MMU_INT_MAIN_CONTROL 0x124 /* below: mmu0 | mmu1 */ > > Other than that, > Reviewed-by: Evan Green <evgreen@chromium.org>
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 66e3615..7fcef19 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -70,27 +70,32 @@ #define F_MISS_FIFO_ERR_INT_EN BIT(6) #define F_INT_CLR_BIT BIT(12) -#define REG_MMU_INT_MAIN_CONTROL 0x124 -#define F_INT_TRANSLATION_FAULT BIT(0) -#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) -#define F_INT_INVALID_PA_FAULT BIT(2) -#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) -#define F_INT_TLB_MISS_FAULT BIT(4) -#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) -#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) +#define REG_MMU_INT_MAIN_CONTROL 0x124 /* mmu0 | mmu1 */ +#define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) +#define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) +#define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) +#define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) +#define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) +#define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) +#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) #define REG_MMU_CPE_DONE 0x12C #define REG_MMU_FAULT_ST1 0x134 +#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) +#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) -#define REG_MMU_FAULT_VA 0x13c +#define REG_MMU0_FAULT_VA 0x13c #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) -#define REG_MMU_INVLD_PA 0x140 -#define REG_MMU_INT_ID 0x150 -#define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) -#define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +#define REG_MMU0_INVLD_PA 0x140 +#define REG_MMU1_FAULT_VA 0x144 +#define REG_MMU1_INVLD_PA 0x148 +#define REG_MMU0_INT_ID 0x150 +#define REG_MMU1_INT_ID 0x154 +#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) +#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) #define MTK_PROTECT_PA_ALIGN 128 @@ -209,13 +214,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) /* Read error info from registers */ int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); - fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); + if (int_state & F_REG_MMU0_FAULT_MASK) { + regval = readl_relaxed(data->base + REG_MMU0_INT_ID); + fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); + fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); + } else { + regval = readl_relaxed(data->base + REG_MMU1_INT_ID); + fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); + fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); + } layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; - fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); - regval = readl_relaxed(data->base + REG_MMU_INT_ID); - fault_larb = F_MMU0_INT_ID_LARB_ID(regval); - fault_port = F_MMU0_INT_ID_PORT_ID(regval); + fault_larb = F_MMU_INT_ID_LARB_ID(regval); + fault_port = F_MMU_INT_ID_PORT_ID(regval); fault_larb = data->plat_data->larbid_remap[fault_larb];
Normally the M4U HW connect EMI with smi. the diagram is like below: EMI | M4U | smi-common | ----------------- | | | | ... larb0 larb1 larb2 larb3 Actually there are 2 mmu cells in the M4U HW, like this diagram: EMI --------- | | mmu0 mmu1 <- M4U | | --------- | smi-common | ----------------- | | | | ... larb0 larb1 larb2 larb3 This patch add support for mmu1. In order to get better performance, we could adjust some larbs go to mmu1 while the others still go to mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220). mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default value of that register is 0 which means all the larbs go to mmu0 defaultly. This is a preparing patch for adjusting SMI_BUS_SEL for mt8183. Signed-off-by: Yong Wu <yong.wu@mediatek.com> --- drivers/iommu/mtk_iommu.c | 47 +++++++++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 18 deletions(-)