[v2,2/3] arm64: dts: hisilicon: hi3670: Add UFS controller support
diff mbox series

Message ID 20190105072859.9134-3-manivannan.sadhasivam@linaro.org
State Deferred
Headers show
Series
  • Add UFS controller support for HI3670 SoC
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Commit Message

Manivannan Sadhasivam Jan. 5, 2019, 7:28 a.m. UTC
Add UFS controller support for HiSilicon HI3670 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

Comments

Thierry Reding Feb. 20, 2019, 11:35 a.m. UTC | #1
On Sat, Jan 05, 2019 at 12:58:58PM +0530, Manivannan Sadhasivam wrote:
> Add UFS controller support for HiSilicon HI3670 SoC.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)

Hi Martin,

it looks like you picked this up into the SCSI tree (perhaps
inadvertently). It's been causing linux-next to fail to build since
Monday (next-20190218) because it references a phandle (&crg_rst)
that's not available.

There's a patch on the mailing lists to add that, but I think at this
point it'd be better if you could drop this from the SCSI tree and we
let the HiSilicon maintainers deal with the dependency in their tree.

Cc'ing Wei and linux-next.

Thierry

> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> index 6ccdf5040ffd..285219dd657f 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> @@ -654,6 +654,24 @@
>  			clock-names = "apb_pclk";
>  		};
>  
> +		/* UFS */
> +		ufs: ufs@ff3c0000 {
> +			compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
> +			/* 0: HCI standard */
> +			/* 1: UFS SYS CTRL */
> +			reg = <0x0 0xff3c0000 0x0 0x1000>,
> +				<0x0 0xff3e0000 0x0 0x1000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
> +				<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
> +			clock-names = "ref_clk", "phy_clk";
> +			freq-table-hz = <0 0>, <0 0>;
> +			/* offset: 0x84; bit: 12 */
> +			resets = <&crg_rst 0x84 12>;
> +			reset-names = "rst";
> +		};
> +
>  		/* SD */
>  		dwmmc1: dwmmc1@ff37f000 {
>  			compatible = "hisilicon,hi3670-dw-mshc";
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Martin K. Petersen Feb. 20, 2019, 2:21 p.m. UTC | #2
Hi Thierry,

> it looks like you picked this up into the SCSI tree (perhaps
> inadvertently). It's been causing linux-next to fail to build since
> Monday (next-20190218) because it references a phandle (&crg_rst)
> that's not available.

I dropped the offending patch from the SCSI tree yesterday. When Stephen
updates -next, things should be fine.
Wei Xu April 15, 2019, 4 p.m. UTC | #3
Hi Manivannan,

On 2/20/2019 2:21 PM, Martin K. Petersen wrote:
> 
> Hi Thierry,
> 
>> it looks like you picked this up into the SCSI tree (perhaps
>> inadvertently). It's been causing linux-next to fail to build since
>> Monday (next-20190218) because it references a phandle (&crg_rst)
>> that's not available.
> 
> I dropped the offending patch from the SCSI tree yesterday. When Stephen
> updates -next, things should be fine.
> 

Thanks!
Applied the dts patch to the hisilicon dts tree.

Best Regards,
Wei

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 6ccdf5040ffd..285219dd657f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -654,6 +654,24 @@ 
 			clock-names = "apb_pclk";
 		};
 
+		/* UFS */
+		ufs: ufs@ff3c0000 {
+			compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
+			/* 0: HCI standard */
+			/* 1: UFS SYS CTRL */
+			reg = <0x0 0xff3c0000 0x0 0x1000>,
+				<0x0 0xff3e0000 0x0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
+				<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+			clock-names = "ref_clk", "phy_clk";
+			freq-table-hz = <0 0>, <0 0>;
+			/* offset: 0x84; bit: 12 */
+			resets = <&crg_rst 0x84 12>;
+			reset-names = "rst";
+		};
+
 		/* SD */
 		dwmmc1: dwmmc1@ff37f000 {
 			compatible = "hisilicon,hi3670-dw-mshc";