[2/5] mmc: sdhci-esdhc-imx: add HS400_ES support for i.MX8QXP
diff mbox series

Message ID 20190107101757.27647-2-haibo.chen@nxp.com
State New
Headers show
Series
  • [1/5] mmc: sdhci-esdhc-imx: remove the 100MHz limitation for Strobe DLL
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Commit Message

BOUGH CHEN Jan. 7, 2019, 10:11 a.m. UTC
Add an new esdhc_soc_data for i.MX8QXP, and add HS400_ES mode
support.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

Comments

Hunter, Adrian Jan. 14, 2019, 8:49 a.m. UTC | #1
On 7/01/19 12:11 PM, BOUGH CHEN wrote:
> Add an new esdhc_soc_data for i.MX8QXP, and add HS400_ES mode
> support.
> 
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 0489b60b8eb4..08bba97706d0 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -52,6 +52,7 @@
>  #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN	(1 << 24)
>  #define  ESDHC_MIX_CTRL_FBCLK_SEL	(1 << 25)
>  #define  ESDHC_MIX_CTRL_HS400_EN	(1 << 26)
> +#define  ESDHC_MIX_CTRL_HS400_ES_EN	(1 << 27)
>  /* Bits 3 and 6 are not SDHCI standard definitions */
>  #define  ESDHC_MIX_CTRL_SDHCI_MASK	0xb7
>  /* Tuning bits */
> @@ -140,6 +141,8 @@
>  #define ESDHC_FLAG_HS200		BIT(8)
>  /* The IP supports HS400 mode */
>  #define ESDHC_FLAG_HS400		BIT(9)
> +/* The IP supports HS400ES mode */
> +#define ESDHC_FLAG_HS400_ES		BIT(10)
>  
>  struct esdhc_soc_data {
>  	u32 flags;
> @@ -182,6 +185,12 @@ static struct esdhc_soc_data usdhc_imx7d_data = {
>  			| ESDHC_FLAG_HS400,
>  };
>  
> +static struct esdhc_soc_data usdhc_imx8qxp_data = {
> +	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
> +			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> +			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
> +};
> +
>  struct pltfm_imx_data {
>  	u32 scratchpad;
>  	struct pinctrl *pinctrl;
> @@ -227,6 +236,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
>  	{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
>  	{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
>  	{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
> +	{ .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
> @@ -863,6 +873,19 @@ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
>  	return ret;
>  }
>  
> +static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	u32 m;
> +
> +	m = readl(host->ioaddr + ESDHC_MIX_CTRL);
> +	if (ios->enhanced_strobe)
> +		m |= ESDHC_MIX_CTRL_HS400_ES_EN;
> +	else
> +		m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
> +	writel(m, host->ioaddr + ESDHC_MIX_CTRL);
> +}
> +
>  static int esdhc_change_pinstate(struct sdhci_host *host,
>  						unsigned int uhs)
>  {
> @@ -1334,6 +1357,12 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
>  	if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
>  		host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
>  
> +	if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
> +		host->mmc->caps2 |= MMC_CAP2_HS400_ES;
> +		host->mmc_host_ops.hs400_enhanced_strobe =
> +					esdhc_hs400_enhanced_strobe;
> +	}
> +
>  	if (of_id)
>  		err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
>  	else
>
Ulf Hansson Jan. 14, 2019, 11:45 a.m. UTC | #2
On Mon, 7 Jan 2019 at 11:11, BOUGH CHEN <haibo.chen@nxp.com> wrote:
>
> Add an new esdhc_soc_data for i.MX8QXP, and add HS400_ES mode
> support.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Applied for next (I re-based it on top of your latest changes), thanks!

Kind regards
Uffe



> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 0489b60b8eb4..08bba97706d0 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -52,6 +52,7 @@
>  #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN   (1 << 24)
>  #define  ESDHC_MIX_CTRL_FBCLK_SEL      (1 << 25)
>  #define  ESDHC_MIX_CTRL_HS400_EN       (1 << 26)
> +#define  ESDHC_MIX_CTRL_HS400_ES_EN    (1 << 27)
>  /* Bits 3 and 6 are not SDHCI standard definitions */
>  #define  ESDHC_MIX_CTRL_SDHCI_MASK     0xb7
>  /* Tuning bits */
> @@ -140,6 +141,8 @@
>  #define ESDHC_FLAG_HS200               BIT(8)
>  /* The IP supports HS400 mode */
>  #define ESDHC_FLAG_HS400               BIT(9)
> +/* The IP supports HS400ES mode */
> +#define ESDHC_FLAG_HS400_ES            BIT(10)
>
>  struct esdhc_soc_data {
>         u32 flags;
> @@ -182,6 +185,12 @@ static struct esdhc_soc_data usdhc_imx7d_data = {
>                         | ESDHC_FLAG_HS400,
>  };
>
> +static struct esdhc_soc_data usdhc_imx8qxp_data = {
> +       .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
> +                       | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> +                       | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
> +};
> +
>  struct pltfm_imx_data {
>         u32 scratchpad;
>         struct pinctrl *pinctrl;
> @@ -227,6 +236,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
>         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
>         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
>         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
> +       { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
> @@ -863,6 +873,19 @@ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
>         return ret;
>  }
>
> +static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
> +{
> +       struct sdhci_host *host = mmc_priv(mmc);
> +       u32 m;
> +
> +       m = readl(host->ioaddr + ESDHC_MIX_CTRL);
> +       if (ios->enhanced_strobe)
> +               m |= ESDHC_MIX_CTRL_HS400_ES_EN;
> +       else
> +               m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
> +       writel(m, host->ioaddr + ESDHC_MIX_CTRL);
> +}
> +
>  static int esdhc_change_pinstate(struct sdhci_host *host,
>                                                 unsigned int uhs)
>  {
> @@ -1334,6 +1357,12 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
>         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
>                 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
>
> +       if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
> +               host->mmc->caps2 |= MMC_CAP2_HS400_ES;
> +               host->mmc_host_ops.hs400_enhanced_strobe =
> +                                       esdhc_hs400_enhanced_strobe;
> +       }
> +
>         if (of_id)
>                 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
>         else
> --
> 2.17.1
>

Patch
diff mbox series

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 0489b60b8eb4..08bba97706d0 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -52,6 +52,7 @@ 
 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN	(1 << 24)
 #define  ESDHC_MIX_CTRL_FBCLK_SEL	(1 << 25)
 #define  ESDHC_MIX_CTRL_HS400_EN	(1 << 26)
+#define  ESDHC_MIX_CTRL_HS400_ES_EN	(1 << 27)
 /* Bits 3 and 6 are not SDHCI standard definitions */
 #define  ESDHC_MIX_CTRL_SDHCI_MASK	0xb7
 /* Tuning bits */
@@ -140,6 +141,8 @@ 
 #define ESDHC_FLAG_HS200		BIT(8)
 /* The IP supports HS400 mode */
 #define ESDHC_FLAG_HS400		BIT(9)
+/* The IP supports HS400ES mode */
+#define ESDHC_FLAG_HS400_ES		BIT(10)
 
 struct esdhc_soc_data {
 	u32 flags;
@@ -182,6 +185,12 @@  static struct esdhc_soc_data usdhc_imx7d_data = {
 			| ESDHC_FLAG_HS400,
 };
 
+static struct esdhc_soc_data usdhc_imx8qxp_data = {
+	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
+};
+
 struct pltfm_imx_data {
 	u32 scratchpad;
 	struct pinctrl *pinctrl;
@@ -227,6 +236,7 @@  static const struct of_device_id imx_esdhc_dt_ids[] = {
 	{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 	{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 	{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
+	{ .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
@@ -863,6 +873,19 @@  static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 	return ret;
 }
 
+static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	u32 m;
+
+	m = readl(host->ioaddr + ESDHC_MIX_CTRL);
+	if (ios->enhanced_strobe)
+		m |= ESDHC_MIX_CTRL_HS400_ES_EN;
+	else
+		m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
+	writel(m, host->ioaddr + ESDHC_MIX_CTRL);
+}
+
 static int esdhc_change_pinstate(struct sdhci_host *host,
 						unsigned int uhs)
 {
@@ -1334,6 +1357,12 @@  static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 	if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
 		host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
 
+	if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
+		host->mmc->caps2 |= MMC_CAP2_HS400_ES;
+		host->mmc_host_ops.hs400_enhanced_strobe =
+					esdhc_hs400_enhanced_strobe;
+	}
+
 	if (of_id)
 		err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
 	else