[02/17] clocksource: davinci-timer: new driver
diff mbox series

Message ID 20190111172134.30147-3-brgl@bgdev.pl
State New
Headers show
Series
  • ARM: davinci: modernize the timer support
Related show

Commit Message

Bartosz Golaszewski Jan. 11, 2019, 5:21 p.m. UTC
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>

Currently the clocksource and clockevent support for davinci platforms
lives in mach-davinci. It hard-codes many things, used global variables,
implements functionalities unused by any platform and has code fragments
scattered across many (often unrelated) files.

Implement a new, modern and simplified timer driver and put it into
drivers/clocksource. We still need to support legacy board files so
export a config structure and a function that allows machine code to
register the timer.

We don't check the return values of regmap reads and writes since with
mmio it's only likely to fail due to programmer's errors.

We also don't bother freeing resources on errors in
davinci_timer_register() as the system won't boot without a timer anyway.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 drivers/clocksource/Kconfig         |   5 +
 drivers/clocksource/Makefile        |   1 +
 drivers/clocksource/timer-davinci.c | 415 ++++++++++++++++++++++++++++
 include/clocksource/timer-davinci.h |  35 +++
 4 files changed, 456 insertions(+)
 create mode 100644 drivers/clocksource/timer-davinci.c
 create mode 100644 include/clocksource/timer-davinci.h

Comments

Sekhar Nori Jan. 14, 2019, 12:20 p.m. UTC | #1
Hi Bartosz,

On 11/01/19 10:51 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> 
> Currently the clocksource and clockevent support for davinci platforms
> lives in mach-davinci. It hard-codes many things, used global variables,
> implements functionalities unused by any platform and has code fragments
> scattered across many (often unrelated) files.
> 
> Implement a new, modern and simplified timer driver and put it into
> drivers/clocksource. We still need to support legacy board files so
> export a config structure and a function that allows machine code to
> register the timer.
> 
> We don't check the return values of regmap reads and writes since with
> mmio it's only likely to fail due to programmer's errors.
> 
> We also don't bother freeing resources on errors in
> davinci_timer_register() as the system won't boot without a timer anyway.
> 
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

With this series, DA830 fails to boot. Rest of the devices are okay from
boot perspective.

DA830 is pretty unique because it uses the same timer-half for both
clocksource and clockevent. May be you can set the same configuration on
your DA850 to see the same issue? Else, I will enable low-level debug
and try to provide more debug data.

Some minor comments below from quick look:

> diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c
> new file mode 100644
> index 000000000000..7282a1fda80f
> --- /dev/null
> +++ b/drivers/clocksource/timer-davinci.c
> @@ -0,0 +1,415 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * TI DaVinci clocksource driver
> + *
> + * Copyright (C) 2019 Texas Instruments
> + * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> + * (with some parts adopted from code by Kevin Hilman <khilman@baylibre.com>)

Did you really intend GPL v2 or later? The original code referred to
above is marked 2.0 only.

> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/clocksource.h>
> +#include <linux/err.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/regmap.h>
> +#include <linux/sched_clock.h>
> +
> +#include <clocksource/timer-davinci.h>
> +
> +#define DAVINCI_TIMER_REG_TIM12			0x10
> +#define DAVINCI_TIMER_REG_TIM34			0x14
> +#define DAVINCI_TIMER_REG_PRD12			0x18
> +#define DAVINCI_TIMER_REG_PRD34			0x1c
> +#define DAVINCI_TIMER_REG_TCR			0x20
> +#define DAVINCI_TIMER_REG_TGCR			0x24
> +
> +#define DAVINCI_TIMER_TIMMODE_MASK		0x0000000c
> +#define DAVINCI_TIMER_RESET_MASK		0x00000003
> +#define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED	0x00000004
> +#define DAVINCI_TIMER_UNRESET			0x00000003

I think these are more readable if using BIT() and GENMASK()

Thanks,
Sekhar
Bartosz Golaszewski Jan. 14, 2019, 4:39 p.m. UTC | #2
pon., 14 sty 2019 o 13:20 Sekhar Nori <nsekhar@ti.com> napisał(a):
>
> Hi Bartosz,
>
> On 11/01/19 10:51 PM, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >
> > Currently the clocksource and clockevent support for davinci platforms
> > lives in mach-davinci. It hard-codes many things, used global variables,
> > implements functionalities unused by any platform and has code fragments
> > scattered across many (often unrelated) files.
> >
> > Implement a new, modern and simplified timer driver and put it into
> > drivers/clocksource. We still need to support legacy board files so
> > export a config structure and a function that allows machine code to
> > register the timer.
> >
> > We don't check the return values of regmap reads and writes since with
> > mmio it's only likely to fail due to programmer's errors.
> >
> > We also don't bother freeing resources on errors in
> > davinci_timer_register() as the system won't boot without a timer anyway.
> >
> > Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>
> With this series, DA830 fails to boot. Rest of the devices are okay from
> boot perspective.
>
> DA830 is pretty unique because it uses the same timer-half for both
> clocksource and clockevent. May be you can set the same configuration on
> your DA850 to see the same issue? Else, I will enable low-level debug
> and try to provide more debug data.
>

I can't boot da850 with the same config as da830 (0x60 compare
register, compare irq 74) even with the old timer code. Just to make
sure: does da830 boot fine with mainline v5.0-rc2?

> Some minor comments below from quick look:
>
> > diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c
> > new file mode 100644
> > index 000000000000..7282a1fda80f
> > --- /dev/null
> > +++ b/drivers/clocksource/timer-davinci.c
> > @@ -0,0 +1,415 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * TI DaVinci clocksource driver
> > + *
> > + * Copyright (C) 2019 Texas Instruments
> > + * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> > + * (with some parts adopted from code by Kevin Hilman <khilman@baylibre.com>)
>
> Did you really intend GPL v2 or later? The original code referred to
> above is marked 2.0 only.
>

I'm not sure. Should it be GPLv2 only? I'm not well versed with licensing.

Bart

> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clockchips.h>
> > +#include <linux/clocksource.h>
> > +#include <linux/err.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/regmap.h>
> > +#include <linux/sched_clock.h>
> > +
> > +#include <clocksource/timer-davinci.h>
> > +
> > +#define DAVINCI_TIMER_REG_TIM12                      0x10
> > +#define DAVINCI_TIMER_REG_TIM34                      0x14
> > +#define DAVINCI_TIMER_REG_PRD12                      0x18
> > +#define DAVINCI_TIMER_REG_PRD34                      0x1c
> > +#define DAVINCI_TIMER_REG_TCR                        0x20
> > +#define DAVINCI_TIMER_REG_TGCR                       0x24
> > +
> > +#define DAVINCI_TIMER_TIMMODE_MASK           0x0000000c
> > +#define DAVINCI_TIMER_RESET_MASK             0x00000003
> > +#define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED        0x00000004
> > +#define DAVINCI_TIMER_UNRESET                        0x00000003
>
> I think these are more readable if using BIT() and GENMASK()
>
> Thanks,
> Sekhar
Sekhar Nori Jan. 16, 2019, 9:18 a.m. UTC | #3
On 14/01/19 10:09 PM, Bartosz Golaszewski wrote:
> pon., 14 sty 2019 o 13:20 Sekhar Nori <nsekhar@ti.com> napisał(a):
>>
>> Hi Bartosz,
>>
>> On 11/01/19 10:51 PM, Bartosz Golaszewski wrote:
>>> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>>
>>> Currently the clocksource and clockevent support for davinci platforms
>>> lives in mach-davinci. It hard-codes many things, used global variables,
>>> implements functionalities unused by any platform and has code fragments
>>> scattered across many (often unrelated) files.
>>>
>>> Implement a new, modern and simplified timer driver and put it into
>>> drivers/clocksource. We still need to support legacy board files so
>>> export a config structure and a function that allows machine code to
>>> register the timer.
>>>
>>> We don't check the return values of regmap reads and writes since with
>>> mmio it's only likely to fail due to programmer's errors.
>>>
>>> We also don't bother freeing resources on errors in
>>> davinci_timer_register() as the system won't boot without a timer anyway.
>>>
>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>
>> With this series, DA830 fails to boot. Rest of the devices are okay from
>> boot perspective.
>>
>> DA830 is pretty unique because it uses the same timer-half for both
>> clocksource and clockevent. May be you can set the same configuration on
>> your DA850 to see the same issue? Else, I will enable low-level debug
>> and try to provide more debug data.
>>
> 
> I can't boot da850 with the same config as da830 (0x60 compare
> register, compare irq 74) even with the old timer code. Just to make
> sure: does da830 boot fine with mainline v5.0-rc2?

Yeah, I did check that without the patch DA830 does boot.

Thanks,
Sekhar
Sekhar Nori Jan. 17, 2019, 12:42 p.m. UTC | #4
On 16/01/19 2:48 PM, Sekhar Nori wrote:
> On 14/01/19 10:09 PM, Bartosz Golaszewski wrote:
>> pon., 14 sty 2019 o 13:20 Sekhar Nori <nsekhar@ti.com> napisał(a):
>>>
>>> Hi Bartosz,
>>>
>>> On 11/01/19 10:51 PM, Bartosz Golaszewski wrote:
>>>> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>>>
>>>> Currently the clocksource and clockevent support for davinci platforms
>>>> lives in mach-davinci. It hard-codes many things, used global variables,
>>>> implements functionalities unused by any platform and has code fragments
>>>> scattered across many (often unrelated) files.
>>>>
>>>> Implement a new, modern and simplified timer driver and put it into
>>>> drivers/clocksource. We still need to support legacy board files so
>>>> export a config structure and a function that allows machine code to
>>>> register the timer.
>>>>
>>>> We don't check the return values of regmap reads and writes since with
>>>> mmio it's only likely to fail due to programmer's errors.
>>>>
>>>> We also don't bother freeing resources on errors in
>>>> davinci_timer_register() as the system won't boot without a timer anyway.
>>>>
>>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>>
>>> With this series, DA830 fails to boot. Rest of the devices are okay from
>>> boot perspective.
>>>
>>> DA830 is pretty unique because it uses the same timer-half for both
>>> clocksource and clockevent. May be you can set the same configuration on
>>> your DA850 to see the same issue? Else, I will enable low-level debug
>>> and try to provide more debug data.
>>>
>>
>> I can't boot da850 with the same config as da830 (0x60 compare
>> register, compare irq 74) even with the old timer code. Just to make
>> sure: does da830 boot fine with mainline v5.0-rc2?
> 
> Yeah, I did check that without the patch DA830 does boot.

You are right that DA850 lacks compare interrupts for timers 0 and 1.
So, yes, it seems like we will have to shift to timer2 to test
compare interrupts on DA850.

Just to confirm, DA830 boots fine with the compare section removed:

---8<---
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 0d81a8fdd9e6..f34398a7e47c 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -788,14 +788,6 @@ static const struct davinci_timer_cfg da830_timer_cfg = {
 			.flags	= IORESOURCE_IRQ,
 		},
 	},
-	.cmp = {
-		.irq = {
-			.start	= IRQ_DA830_T12CMPINT0_0,
-			.end	= IRQ_DA830_T12CMPINT0_0,
-			.flags	= IORESOURCE_IRQ,
-		},
-		.offset		= DA830_CMP12_0,
-	}
 };
 
 static const struct davinci_soc_info davinci_soc_info_da830 = {
---8<---

And the low-level debug with your patches shows that its hanging at 
delay loop calibration.

Uncompressing Linux... done, booting the kernel.                                
Booting Linux on physical CPU 0x0                                               
Linux version 5.0.0-rc1-08699-gc87d386784f3-dirty (a0875516@psplinux063) (gcc v9
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=0005317f                   
CPU: VIVT data cache, VIVT instruction cache                                    
Machine: DaVinci DA830/OMAP-L137/AM17x EVM                                      
Memory policy: Data cache writethrough                                          
cma: Reserved 16 MiB at 0xc2800000                                              
DaVinci da830/omap-l137 rev2.0 variant 0x9                                      
On node 0 totalpages: 14336                                                     
  DMA zone: 112 pages used for memmap                                           
  DMA zone: 0 pages reserved                                                    
  DMA zone: 14336 pages, LIFO batch:3                                           
random: get_random_bytes called from start_kernel+0x80/0x3ec with crng_init=0   
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768                                   
pcpu-alloc: [0] 0                                                               
Built 1 zonelists, mobility grouping on.  Total pages: 14224                    
Kernel command line: console=ttyS2,115200n8                                     
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)                   
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)                    
Memory: 33876K/57344K available (4607K kernel code, 308K rwdata, 1072K rodata, )
Virtual kernel memory layout:                                                   
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)                               
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)                               
    vmalloc : 0xc4000000 - 0xff800000   ( 952 MB)                               
    lowmem  : 0xc0000000 - 0xc3800000   (  56 MB)                               
    modules : 0xbf000000 - 0xc0000000   (  16 MB)                               
      .text : 0x(ptrval) - 0x(ptrval)   (4609 kB)                               
      .init : 0x(ptrval) - 0x(ptrval)   ( 212 kB)                               
      .data : 0x(ptrval) - 0x(ptrval)   ( 309 kB)                               
       .bss : 0x(ptrval) - 0x(ptrval)   ( 137 kB)                               
SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1                      
rcu: Preemptible hierarchical RCU implementation.                               
        Tasks RCU enabled.                                                      
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.          
NR_IRQS: 245                                                                    
clocksource: timer0_0: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79s
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns       
Console: colour dummy device 80x30                                              
Calibrating delay loop... 
<hangs>

Thanks,
Sekhar
Bartosz Golaszewski Jan. 17, 2019, 2:01 p.m. UTC | #5
czw., 17 sty 2019 o 13:42 Sekhar Nori <nsekhar@ti.com> napisał(a):
>
> On 16/01/19 2:48 PM, Sekhar Nori wrote:
> > On 14/01/19 10:09 PM, Bartosz Golaszewski wrote:
> >> pon., 14 sty 2019 o 13:20 Sekhar Nori <nsekhar@ti.com> napisał(a):
> >>>
> >>> Hi Bartosz,
> >>>
> >>> On 11/01/19 10:51 PM, Bartosz Golaszewski wrote:
> >>>> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >>>>
> >>>> Currently the clocksource and clockevent support for davinci platforms
> >>>> lives in mach-davinci. It hard-codes many things, used global variables,
> >>>> implements functionalities unused by any platform and has code fragments
> >>>> scattered across many (often unrelated) files.
> >>>>
> >>>> Implement a new, modern and simplified timer driver and put it into
> >>>> drivers/clocksource. We still need to support legacy board files so
> >>>> export a config structure and a function that allows machine code to
> >>>> register the timer.
> >>>>
> >>>> We don't check the return values of regmap reads and writes since with
> >>>> mmio it's only likely to fail due to programmer's errors.
> >>>>
> >>>> We also don't bother freeing resources on errors in
> >>>> davinci_timer_register() as the system won't boot without a timer anyway.
> >>>>
> >>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >>>
> >>> With this series, DA830 fails to boot. Rest of the devices are okay from
> >>> boot perspective.
> >>>
> >>> DA830 is pretty unique because it uses the same timer-half for both
> >>> clocksource and clockevent. May be you can set the same configuration on
> >>> your DA850 to see the same issue? Else, I will enable low-level debug
> >>> and try to provide more debug data.
> >>>
> >>
> >> I can't boot da850 with the same config as da830 (0x60 compare
> >> register, compare irq 74) even with the old timer code. Just to make
> >> sure: does da830 boot fine with mainline v5.0-rc2?
> >
> > Yeah, I did check that without the patch DA830 does boot.
>
> You are right that DA850 lacks compare interrupts for timers 0 and 1.
> So, yes, it seems like we will have to shift to timer2 to test
> compare interrupts on DA850.
>

Timers 2 and 3 are a bit different on da850 - for instance they don't
have separate interrupts for bottom and top halfs.

I configured the old code to use timer 2 - bottom half only with
compare register 0x60 and compare intterupt 74. It boots although very
slowly and something's broken with timekeeping as the clock goes
backwards and forward (seemingly) randomly.

Kevin has an OMAP-L137 starter kit - is this the same as da830-evm? If
so, then I can get remote access to it and work on this problem.
Otherwise, I can prepare something that works on da850 with broken
timekeeping and let you see if it works correctly on da830.

Bart

> Just to confirm, DA830 boots fine with the compare section removed:
>
> ---8<---
> diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
> index 0d81a8fdd9e6..f34398a7e47c 100644
> --- a/arch/arm/mach-davinci/da830.c
> +++ b/arch/arm/mach-davinci/da830.c
> @@ -788,14 +788,6 @@ static const struct davinci_timer_cfg da830_timer_cfg = {
>                         .flags  = IORESOURCE_IRQ,
>                 },
>         },
> -       .cmp = {
> -               .irq = {
> -                       .start  = IRQ_DA830_T12CMPINT0_0,
> -                       .end    = IRQ_DA830_T12CMPINT0_0,
> -                       .flags  = IORESOURCE_IRQ,
> -               },
> -               .offset         = DA830_CMP12_0,
> -       }
>  };
>
>  static const struct davinci_soc_info davinci_soc_info_da830 = {
> ---8<---
>
> And the low-level debug with your patches shows that its hanging at
> delay loop calibration.
>
> Uncompressing Linux... done, booting the kernel.
> Booting Linux on physical CPU 0x0
> Linux version 5.0.0-rc1-08699-gc87d386784f3-dirty (a0875516@psplinux063) (gcc v9
> CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=0005317f
> CPU: VIVT data cache, VIVT instruction cache
> Machine: DaVinci DA830/OMAP-L137/AM17x EVM
> Memory policy: Data cache writethrough
> cma: Reserved 16 MiB at 0xc2800000
> DaVinci da830/omap-l137 rev2.0 variant 0x9
> On node 0 totalpages: 14336
>   DMA zone: 112 pages used for memmap
>   DMA zone: 0 pages reserved
>   DMA zone: 14336 pages, LIFO batch:3
> random: get_random_bytes called from start_kernel+0x80/0x3ec with crng_init=0
> pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
> pcpu-alloc: [0] 0
> Built 1 zonelists, mobility grouping on.  Total pages: 14224
> Kernel command line: console=ttyS2,115200n8
> Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
> Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
> Memory: 33876K/57344K available (4607K kernel code, 308K rwdata, 1072K rodata, )
> Virtual kernel memory layout:
>     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
>     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
>     vmalloc : 0xc4000000 - 0xff800000   ( 952 MB)
>     lowmem  : 0xc0000000 - 0xc3800000   (  56 MB)
>     modules : 0xbf000000 - 0xc0000000   (  16 MB)
>       .text : 0x(ptrval) - 0x(ptrval)   (4609 kB)
>       .init : 0x(ptrval) - 0x(ptrval)   ( 212 kB)
>       .data : 0x(ptrval) - 0x(ptrval)   ( 309 kB)
>        .bss : 0x(ptrval) - 0x(ptrval)   ( 137 kB)
> SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
> rcu: Preemptible hierarchical RCU implementation.
>         Tasks RCU enabled.
> rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
> NR_IRQS: 245
> clocksource: timer0_0: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79s
> sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
> Console: colour dummy device 80x30
> Calibrating delay loop...
> <hangs>
>
> Thanks,
> Sekhar

Patch
diff mbox series

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a9e26f6a81a1..36d222c3fa4a 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -42,6 +42,11 @@  config BCM_KONA_TIMER
 	help
 	  Enables the support for the BCM Kona mobile timer driver.
 
+config DAVINCI_TIMER
+	bool "Texas Instruments DaVinci timer driver"
+	help
+	  Enables the support for the TI DaVinci timer driver.
+
 config DIGICOLOR_TIMER
 	bool "Digicolor timer driver" if COMPILE_TEST
 	select CLKSRC_MMIO
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index cdd210ff89ea..1be97aa7a699 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -15,6 +15,7 @@  obj-$(CONFIG_SH_TIMER_TMU)	+= sh_tmu.o
 obj-$(CONFIG_EM_TIMER_STI)	+= em_sti.o
 obj-$(CONFIG_CLKBLD_I8253)	+= i8253.o
 obj-$(CONFIG_CLKSRC_MMIO)	+= mmio.o
+obj-$(CONFIG_DAVINCI_TIMER)	+= timer-davinci.o
 obj-$(CONFIG_DIGICOLOR_TIMER)	+= timer-digicolor.o
 obj-$(CONFIG_OMAP_DM_TIMER)	+= timer-ti-dm.o
 obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c
new file mode 100644
index 000000000000..7282a1fda80f
--- /dev/null
+++ b/drivers/clocksource/timer-davinci.c
@@ -0,0 +1,415 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI DaVinci clocksource driver
+ *
+ * Copyright (C) 2019 Texas Instruments
+ * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+ * (with some parts adopted from code by Kevin Hilman <khilman@baylibre.com>)
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/regmap.h>
+#include <linux/sched_clock.h>
+
+#include <clocksource/timer-davinci.h>
+
+#define DAVINCI_TIMER_REG_TIM12			0x10
+#define DAVINCI_TIMER_REG_TIM34			0x14
+#define DAVINCI_TIMER_REG_PRD12			0x18
+#define DAVINCI_TIMER_REG_PRD34			0x1c
+#define DAVINCI_TIMER_REG_TCR			0x20
+#define DAVINCI_TIMER_REG_TGCR			0x24
+
+#define DAVINCI_TIMER_TIMMODE_MASK		0x0000000c
+#define DAVINCI_TIMER_RESET_MASK		0x00000003
+#define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED	0x00000004
+#define DAVINCI_TIMER_UNRESET			0x00000003
+
+/* Shift depends on timer. */
+#define DAVINCI_TIMER_ENAMODE_MASK		0x03
+#define DAVINCI_TIMER_ENAMODE_DISABLED		0x00
+#define DAVINCI_TIMER_ENAMODE_ONESHOT		0x01
+#define DAVINCI_TIMER_ENAMODE_PERIODIC		0x02
+
+#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM12	6
+#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM34	22
+
+#define DAVINCI_TIMER_MIN_DELTA			0x01
+#define DAVINCI_TIMER_MAX_DELTA			0xfffffffe
+
+#define DAVINCI_TIMER_CLKSRC_BITS		32
+
+enum {
+	DAVINCI_TIMER_MODE_DISABLED = 0,
+	DAVINCI_TIMER_MODE_ONESHOT,
+	DAVINCI_TIMER_MODE_PERIODIC,
+};
+
+struct davinci_timer_data;
+
+typedef void (*davinci_timer_set_period_func)(struct davinci_timer_data *,
+					      unsigned int period);
+
+struct davinci_timer_regs {
+	unsigned int tim_off;
+	unsigned int prd_off;
+	unsigned int enamode_shift;
+};
+
+struct davinci_timer_data {
+	const struct davinci_timer_regs *regs;
+	unsigned int mode;
+	struct regmap *map;
+	davinci_timer_set_period_func set_period;
+	unsigned int cmp_off;
+};
+
+struct davinci_timer_clockevent {
+	struct clock_event_device dev;
+	unsigned int tick_rate;
+	struct davinci_timer_data timer;
+};
+
+struct davinci_timer_clocksource {
+	struct clocksource dev;
+	struct davinci_timer_data timer;
+};
+
+static const struct regmap_config davinci_timer_regmap_config = {
+	.name			= "timer-davinci",
+	.reg_bits		= 32,
+	.reg_stride		= 4,
+	.val_bits		= 32,
+	.fast_io		= true,
+};
+
+static const struct davinci_timer_regs davinci_timer_tim12_regs = {
+	.tim_off		= DAVINCI_TIMER_REG_TIM12,
+	.prd_off		= DAVINCI_TIMER_REG_PRD12,
+	.enamode_shift		= DAVINCI_TIMER_ENAMODE_SHIFT_TIM12,
+};
+
+static const struct davinci_timer_regs davinci_timer_tim34_regs = {
+	.tim_off		= DAVINCI_TIMER_REG_TIM34,
+	.prd_off		= DAVINCI_TIMER_REG_PRD34,
+	.enamode_shift		= DAVINCI_TIMER_ENAMODE_SHIFT_TIM34,
+};
+
+/* Must be global for davinci_timer_read_sched_clock(). */
+static struct davinci_timer_data *davinci_timer_clksrc_timer;
+
+static struct davinci_timer_clockevent *
+to_davinci_timer_clockevent(struct clock_event_device *clockevent)
+{
+	return container_of(clockevent, struct davinci_timer_clockevent, dev);
+}
+
+static struct davinci_timer_clocksource *
+to_davinci_timer_clocksource(struct clocksource *clocksource)
+{
+	return container_of(clocksource, struct davinci_timer_clocksource, dev);
+}
+
+static void davinci_timer_set_period(struct davinci_timer_data *timer,
+				     unsigned int period)
+{
+	timer->set_period(timer, period);
+}
+
+static void davinci_timer_set_period_std(struct davinci_timer_data *timer,
+					 unsigned int period)
+{
+	const struct davinci_timer_regs *regs = timer->regs;
+	unsigned int enamode;
+
+	regmap_read(timer->map, DAVINCI_TIMER_REG_TCR, &enamode);
+
+	regmap_update_bits(timer->map, DAVINCI_TIMER_REG_TCR,
+			DAVINCI_TIMER_ENAMODE_MASK << regs->enamode_shift,
+			DAVINCI_TIMER_ENAMODE_DISABLED << regs->enamode_shift);
+
+	regmap_write(timer->map, regs->tim_off, 0x0);
+	regmap_write(timer->map, regs->prd_off, period);
+
+	if (timer->mode == DAVINCI_TIMER_MODE_ONESHOT)
+		enamode = DAVINCI_TIMER_ENAMODE_ONESHOT;
+	else if (timer->mode == DAVINCI_TIMER_MODE_PERIODIC)
+		enamode = DAVINCI_TIMER_ENAMODE_PERIODIC;
+
+	regmap_update_bits(timer->map, DAVINCI_TIMER_REG_TCR,
+			   DAVINCI_TIMER_ENAMODE_MASK << regs->enamode_shift,
+			   enamode << regs->enamode_shift);
+}
+
+static void davinci_timer_set_period_cmp(struct davinci_timer_data *timer,
+					 unsigned int period)
+{
+	const struct davinci_timer_regs *regs = timer->regs;
+	unsigned int curr_time;
+
+	regmap_read(timer->map, regs->tim_off, &curr_time);
+	regmap_write(timer->map, timer->cmp_off, curr_time + period);
+}
+
+static irqreturn_t davinci_timer_irq_timer(int irq, void *data)
+{
+	struct davinci_timer_clockevent *clockevent = data;
+
+	clockevent->dev.event_handler(&clockevent->dev);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t davinci_timer_irq_freerun(int irq, void *data)
+{
+	return IRQ_HANDLED;
+}
+
+static u64 notrace davinci_timer_read_sched_clock(void)
+{
+	struct davinci_timer_data *timer;
+	unsigned int val;
+
+	timer = davinci_timer_clksrc_timer;
+	regmap_read(timer->map, timer->regs->tim_off, &val);
+
+	return val;
+}
+
+static u64 davinci_timer_read(struct clocksource *dev)
+{
+	struct davinci_timer_clocksource *clocksource;
+	const struct davinci_timer_regs *regs;
+	unsigned int val;
+
+	clocksource = to_davinci_timer_clocksource(dev);
+	regs = clocksource->timer.regs;
+
+	regmap_read(clocksource->timer.map, regs->tim_off, &val);
+
+	return val;
+}
+
+static int davinci_timer_set_next_event(unsigned long cycles,
+					struct clock_event_device *dev)
+{
+	struct davinci_timer_clockevent *clockevent;
+
+	clockevent = to_davinci_timer_clockevent(dev);
+	davinci_timer_set_period(&clockevent->timer, cycles);
+
+	return 0;
+}
+
+static int davinci_timer_set_state_shutdown(struct clock_event_device *dev)
+{
+	struct davinci_timer_clockevent *clockevent;
+
+	clockevent = to_davinci_timer_clockevent(dev);
+	clockevent->timer.mode = DAVINCI_TIMER_MODE_DISABLED;
+
+	return 0;
+}
+
+static int davinci_timer_set_state_periodic(struct clock_event_device *dev)
+{
+	struct davinci_timer_clockevent *clockevent;
+	unsigned int period;
+
+	clockevent = to_davinci_timer_clockevent(dev);
+	period = clockevent->tick_rate / HZ;
+
+	clockevent->timer.mode = DAVINCI_TIMER_MODE_PERIODIC;
+	davinci_timer_set_period(&clockevent->timer, period);
+
+	return 0;
+}
+
+static int davinci_timer_set_state_oneshot(struct clock_event_device *dev)
+{
+	struct davinci_timer_clockevent *clockevent;
+
+	clockevent = to_davinci_timer_clockevent(dev);
+	clockevent->timer.mode = DAVINCI_TIMER_MODE_ONESHOT;
+
+	return 0;
+}
+
+int __init davinci_timer_register(struct clk *clk,
+				  const struct davinci_timer_cfg *timer_cfg)
+{
+	struct davinci_timer_clocksource *clocksource;
+	struct davinci_timer_clockevent *clockevent;
+	struct regmap *map;
+	int rv, clkev_irq;
+	void *base;
+
+	rv = clk_prepare_enable(clk);
+	if (rv) {
+		pr_err("%s: Unable to prepare and enable the timer clock\n",
+		       __func__);
+		return rv;
+	}
+
+	base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg));
+	if (!base) {
+		pr_err("%s: Unable to map the register range", __func__);
+		return -ENOMEM;
+	}
+
+	map = regmap_init_mmio(NULL, base, &davinci_timer_regmap_config);
+	if (IS_ERR(map)) {
+		pr_err("%s: Error initiating regmap\n", __func__);
+		return PTR_ERR(map);
+	}
+
+	/* Global timer init. */
+
+	/* Set clock to internal mode and disable it. */
+	regmap_write(map, DAVINCI_TIMER_REG_TCR, 0x0);
+	/* Reset both 32-bit timers, set no prescaler for timer 34. */
+	regmap_write(map, DAVINCI_TIMER_REG_TGCR, 0x0);
+	/* Set the timer to dual 32-bit unchained mode. */
+	regmap_update_bits(map, DAVINCI_TIMER_REG_TGCR,
+			   DAVINCI_TIMER_TIMMODE_MASK,
+			   DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED);
+	/* Unreset both 32-bit timers. */
+	regmap_update_bits(map, DAVINCI_TIMER_REG_TGCR,
+			   DAVINCI_TIMER_RESET_MASK, DAVINCI_TIMER_UNRESET);
+	/* Init both counters to zero. */
+	regmap_write(map, DAVINCI_TIMER_REG_TIM12, 0x0);
+	regmap_write(map, DAVINCI_TIMER_REG_TIM34, 0x0);
+
+	/* Setup clockevent. */
+
+	clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL);
+	if (!clockevent) {
+		pr_err("%s: Error allocating memory for clockevent data",
+		       __func__);
+		return -ENOMEM;
+	}
+
+	clockevent->dev.name = "timer0_0";
+	clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT;
+	clockevent->dev.set_next_event = davinci_timer_set_next_event;
+	clockevent->dev.set_state_shutdown = davinci_timer_set_state_shutdown;
+	clockevent->dev.set_state_periodic = davinci_timer_set_state_periodic;
+	clockevent->dev.set_state_oneshot = davinci_timer_set_state_oneshot;
+	clockevent->dev.cpumask = cpumask_of(0);
+	clockevent->tick_rate = clk_get_rate(clk);
+	clockevent->timer.mode = DAVINCI_TIMER_MODE_DISABLED;
+	clockevent->timer.map = map;
+	clockevent->timer.regs = &davinci_timer_tim12_regs;
+
+	if (timer_cfg->cmp.offset) {
+		clkev_irq = timer_cfg->cmp.irq.start;
+		clockevent->timer.cmp_off = timer_cfg->cmp.offset;
+		clockevent->timer.set_period = davinci_timer_set_period_cmp;
+	} else {
+		clkev_irq = timer_cfg->irq[DAVINCI_TIMER_TIM12_IRQ].start;
+		clockevent->dev.features |= CLOCK_EVT_FEAT_PERIODIC;
+		clockevent->timer.set_period = davinci_timer_set_period_std;
+	}
+
+	rv = request_irq(clkev_irq, davinci_timer_irq_timer,
+			 IRQF_TIMER, "clockevent", clockevent);
+	if (rv) {
+		pr_err("%s: Unable to request the clockevent interrupt\n",
+		       __func__);
+		return rv;
+	}
+
+	clockevents_config_and_register(&clockevent->dev,
+					clockevent->tick_rate,
+					DAVINCI_TIMER_MIN_DELTA,
+					DAVINCI_TIMER_MAX_DELTA);
+
+	/* Setup clocksource */
+
+	clocksource = kzalloc(sizeof(*clocksource), GFP_KERNEL);
+	if (!clocksource) {
+		pr_err("%s: Error allocating memory for clocksource data",
+		       __func__);
+		return -ENOMEM;
+	}
+
+	clocksource->dev.name = timer_cfg->cmp.offset ? "timer0_0" : "timer0_1";
+	clocksource->dev.rating = 300;
+	clocksource->dev.read = davinci_timer_read;
+	clocksource->dev.mask = CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS);
+	clocksource->dev.flags = CLOCK_SOURCE_IS_CONTINUOUS;
+	clocksource->timer.set_period = davinci_timer_set_period_std;
+	clocksource->timer.mode = DAVINCI_TIMER_MODE_PERIODIC;
+	clocksource->timer.map = map;
+	clocksource->timer.regs = &davinci_timer_tim34_regs;
+
+	rv = request_irq(timer_cfg->irq[DAVINCI_TIMER_TIM34_IRQ].start,
+			 davinci_timer_irq_freerun, IRQF_TIMER,
+			 "free-run counter", clocksource);
+	if (rv) {
+		pr_err("%s: Unable to request the clocksource interrupt\n",
+		       __func__);
+		return rv;
+	}
+
+	rv = clocksource_register_hz(&clocksource->dev, clockevent->tick_rate);
+	if (rv) {
+		pr_err("%s: Unable to register clocksource\n",
+		       __func__);
+		return rv;
+	}
+
+	davinci_timer_clksrc_timer = &clocksource->timer;
+
+	sched_clock_register(davinci_timer_read_sched_clock,
+			     DAVINCI_TIMER_CLKSRC_BITS,
+			     clockevent->tick_rate);
+
+	davinci_timer_set_period(&clockevent->timer,
+				 clockevent->tick_rate / HZ);
+	davinci_timer_set_period(&clocksource->timer, UINT_MAX);
+
+	return 0;
+}
+
+static int __init of_davinci_timer_register(struct device_node *np)
+{
+	struct davinci_timer_cfg timer_cfg = { };
+	struct clk *clk;
+	int rv;
+
+	rv = of_address_to_resource(np, 0, &timer_cfg.reg);
+	if (rv) {
+		pr_err("%s: Unable to get the register range for timer\n",
+		       __func__);
+		return rv;
+	}
+
+	rv = of_irq_to_resource_table(np, timer_cfg.irq,
+				      DAVINCI_TIMER_NUM_IRQS);
+	if (rv != DAVINCI_TIMER_NUM_IRQS) {
+		pr_err("%s: Unable to get the interrupts for timer\n",
+		       __func__);
+		return rv;
+	}
+
+	clk = of_clk_get(np, 0);
+	if (IS_ERR(clk)) {
+		pr_err("%s: Unable to get the timer clock\n", __func__);
+		return PTR_ERR(clk);
+	}
+
+	rv = davinci_timer_register(clk, &timer_cfg);
+	if (rv)
+		clk_put(clk);
+
+	return rv;
+}
+TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_register);
diff --git a/include/clocksource/timer-davinci.h b/include/clocksource/timer-davinci.h
new file mode 100644
index 000000000000..77a98cbd040b
--- /dev/null
+++ b/include/clocksource/timer-davinci.h
@@ -0,0 +1,35 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * TI DaVinci clocksource driver
+ *
+ * Copyright (C) 2019 Texas Instruments
+ * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+ */
+
+#ifndef __TIMER_DAVINCI_H__
+#define __TIMER_DAVINCI_H__
+
+#include <linux/clk.h>
+#include <linux/ioport.h>
+
+enum {
+	DAVINCI_TIMER_TIM12_IRQ = 0,
+	DAVINCI_TIMER_TIM34_IRQ,
+	DAVINCI_TIMER_NUM_IRQS,
+};
+
+struct davinci_timer_cmp_cfg {
+	struct resource irq;
+	unsigned int offset;
+};
+
+struct davinci_timer_cfg {
+	struct resource reg;
+	struct resource irq[DAVINCI_TIMER_NUM_IRQS];
+	struct davinci_timer_cmp_cfg cmp;
+};
+
+int __init davinci_timer_register(struct clk *clk,
+				  const struct davinci_timer_cfg *data);
+
+#endif /* __TIMER_DAVINCI_H__ */