[03/24] dt-bindings: PCI: keystone: Add "reg-names" binding information
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Message ID 20190114132424.6445-4-kishon@ti.com
State New
Headers show
Series
  • Add support for PCIe RC and EP mode in TI's AM654 SoC
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Commit Message

Kishon Vijay Abraham I Jan. 14, 2019, 1:24 p.m. UTC
Add "reg-names" binding information in order for device tree node
to be populated with the correct register strings. This will break
old dt compatibility. However Keystone PCI has never worked
in upstream kernel due to lack of SERDES support. Before SERDES
support is added, cleanup the Keystone PCI dt-bindngs. This new
binding will also be used by PCI in AM654 platform.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Rob Herring Jan. 22, 2019, 12:31 a.m. UTC | #1
On Mon, 14 Jan 2019 18:54:03 +0530, Kishon Vijay Abraham I wrote:
> Add "reg-names" binding information in order for device tree node
> to be populated with the correct register strings. This will break
> old dt compatibility. However Keystone PCI has never worked
> in upstream kernel due to lack of SERDES support. Before SERDES
> support is added, cleanup the Keystone PCI dt-bindngs. This new
> binding will also be used by PCI in AM654 platform.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
index 2030ee0dc4f9..3a551687cfa2 100644
--- a/Documentation/devicetree/bindings/pci/pci-keystone.txt
+++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
@@ -12,8 +12,10 @@  described here as well as properties that are not applicable.
 Required Properties:-
 
 compatibility: "ti,keystone-pcie"
-reg:	index 1 is the base address and length of DW application registers.
-	index 2 is the base address and length of PCI device ID register.
+reg: Three register ranges as listed in the reg-names property
+reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
+	   TI specific application registers, "config" for the
+	   configuration space address
 
 pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
 	interrupt-cells: should be set to 1