[kvm-unit-test,nVMX] : Check VM-exit MSR-load address on vmentry of L2 guests
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Message ID 20190115171444.18766-1-krish.sadhukhan@oracle.com
State New
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  • [kvm-unit-test,nVMX] : Check VM-exit MSR-load address on vmentry of L2 guests
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Commit Message

Krish Sadhukhan Jan. 15, 2019, 5:14 p.m. UTC
According to section "Checks on VMX Controls" in Intel SDM vol 3C, the
following checks performed for the VM-exit MSR-load address if the
the VM-exit MSR-load count field is non-zero:

    - The lower 4 bits of the VM-exit MSR-load address must be 0.
      The address should not set any bits beyond the processor’s
      physical-address width.

    - The address of the last byte in the VM-exit MSR-load area
      should not set any bits beyond the processor’s physical-address
      width. The address of this last byte is VM-exit MSR-load address
      + (MSR count * 16) - 1. (The arithmetic used for the computation
      uses more bits than the processor’s physical-address width.)

      If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits
      in the range 63:32.

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Reviewed-by: Karl Heubaum <karl.heubaum@oracle.com>
---
 x86/vmx_tests.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

Patch
diff mbox series

diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c
index ee0c9ff..771b508 100644
--- a/x86/vmx_tests.c
+++ b/x86/vmx_tests.c
@@ -4804,6 +4804,75 @@  static void test_vmx_preemption_timer(void)
 	vmcs_write(EXI_CONTROLS, saved_exit);
 }
 
+/*
+ * The following checks are performed for the VM-exit MSR-load address if
+ * the VM-exit MSR-load count field is non-zero:
+ *
+ *    - The lower 4 bits of the VM-exit MSR-load address must be 0.
+ *      The address should not set any bits beyond the processor’s
+ *      physical-address width.
+ *
+ *    - The address of the last byte in the VM-exit MSR-load area
+ *      should not set any bits beyond the processor’s physical-address
+ *      width. The address of this last byte is VM-exit MSR-load address
+ *      + (MSR count * 16) - 1. (The arithmetic used for the computation
+ *      uses more bits than the processor’s physical-address width.)
+ *
+ * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits
+ * in the range 63:32.
+ *
+ *  [Intel SDM]
+ */
+static void test_exit_msr_load(void)
+{
+	exit_msr_load = alloc_page();
+	u64 tmp;
+	u32 exit_msr_ld_cnt = 1;
+	int i;
+	u32 addr_len = 64;
+
+	vmcs_write(EXI_MSR_LD_CNT, exit_msr_ld_cnt);
+
+	/* Check first 4 bits of VM-exit MSR-load address */
+	for (i = 0; i < 4; i++) {
+		tmp = (u64)exit_msr_load | 1ull << i;
+		vmcs_write(EXIT_MSR_LD_ADDR, tmp);
+		report_prefix_pushf("VM-exit MSR-load addr [4:0] %lx",
+				    tmp & 0xf);
+		test_vmx_controls(false, false);
+		report_prefix_pop();
+	}
+
+	if (basic.val & (1ul << 48))
+		addr_len = 32;
+
+	test_vmcs_addr_values("VM-exit-MSR-load address",
+				EXIT_MSR_LD_ADDR, 16, false, false,
+				4, addr_len - 1);
+
+	/*
+	 * Check last byte of VM-exit MSR-load address
+	 */
+	exit_msr_load = (struct vmx_msr_entry *)((u64)exit_msr_load & ~0xf);
+
+	for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len);
+							i < 64; i++) {
+		tmp = ((u64)exit_msr_load + exit_msr_ld_cnt * 16 - 1) |
+			1ul << i;
+		vmcs_write(EXIT_MSR_LD_ADDR,
+			   tmp - (exit_msr_ld_cnt * 16 - 1));
+                test_vmx_controls(false, false);
+	}
+
+	vmcs_write(EXI_MSR_LD_CNT, 2);
+	vmcs_write(EXIT_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16);
+	test_vmx_controls(false, false);
+	vmcs_write(EXIT_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32);
+	test_vmx_controls(true, false);
+	vmcs_write(EXIT_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48);
+	test_vmx_controls(true, false);
+}
+
 /*
  * Tests for VM-execution control fields
  */
@@ -4907,6 +4976,7 @@  static void test_exit_msr_store(void)
 static void test_vm_exit_ctls(void)
 {
 	test_exit_msr_store();
+	test_exit_msr_load();
 }
 
 /*