[4/6] spi: spi-geni-qcom: Add interconnect support
diff mbox series

Message ID 1548138816-1149-5-git-send-email-alokc@codeaurora.org
State New, archived
Headers show
Series
  • Add interconnect support for GENI QUPs
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Commit Message

Alok Chauhan Jan. 22, 2019, 6:33 a.m. UTC
Get the interconnect paths for SPI based Serial Engine device
and vote accordingly based on maximum supported SPI frequency.

Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
---
 drivers/spi/spi-geni-qcom.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

Comments

Mark Brown Jan. 22, 2019, 8:29 p.m. UTC | #1
On Tue, Jan 22, 2019 at 12:03:34PM +0530, Alok Chauhan wrote:

> Get the interconnect paths for SPI based Serial Engine device
> and vote accordingly based on maximum supported SPI frequency.

Still not seeing anything except this patch here in my inbox - like I
said what's the story with dependencies?
Alok Chauhan Jan. 23, 2019, 7:15 a.m. UTC | #2
On 2019-01-23 01:59, Mark Brown wrote:
> On Tue, Jan 22, 2019 at 12:03:34PM +0530, Alok Chauhan wrote:
> 
>> Get the interconnect paths for SPI based Serial Engine device
>> and vote accordingly based on maximum supported SPI frequency.
> 
> Still not seeing anything except this patch here in my inbox - like I
> said what's the story with dependencies?

I've added linux-spi mailing list to all the patches sent as part of 
this series. Not sure why you didn't get other patches. Today I've 
explicitly added you in all the patches.
This change series basically enabled interconnect (as per 
bindings/interconnect/interconnect.txt) support in GENI QUPs based 
drivers so appropriate BW request can be put based on SE usages.
here is my complete change series: 
https://lore.kernel.org/lkml/1548069703-26595-1-git-send-email-alokc@codeaurora.org/
I hope I answer to your question properly.
Mark Brown Jan. 23, 2019, 10:58 a.m. UTC | #3
On Wed, Jan 23, 2019 at 12:45:30PM +0530, alokc@codeaurora.org wrote:
> On 2019-01-23 01:59, Mark Brown wrote:

> > Still not seeing anything except this patch here in my inbox - like I
> > said what's the story with dependencies?

> I've added linux-spi mailing list to all the patches sent as part of this
> series. Not sure why you didn't get other patches. Today I've explicitly
> added you in all the patches.

You really need to ensure that things end up in people's inboxes -
sending them to a mailing list usually means they'll go to a completely
different folder.

> This change series basically enabled interconnect (as per
> bindings/interconnect/interconnect.txt) support in GENI QUPs based drivers
> so appropriate BW request can be put based on SE usages.
> here is my complete change series: https://lore.kernel.org/lkml/1548069703-26595-1-git-send-email-alokc@codeaurora.org/
> I hope I answer to your question properly.

So it looks like there is a dependency on earlier patches in the series,
that's what I needed to know.
Mark Brown Jan. 23, 2019, 4:04 p.m. UTC | #4
On Tue, Jan 22, 2019 at 12:03:34PM +0530, Alok Chauhan wrote:
> Get the interconnect paths for SPI based Serial Engine device
> and vote accordingly based on maximum supported SPI frequency.

Acked-by: Mark Brown <broonie@kernel.org>
Evan Green Jan. 24, 2019, 1:20 a.m. UTC | #5
On Mon, Jan 21, 2019 at 10:34 PM Alok Chauhan <alokc@codeaurora.org> wrote:
>
> Get the interconnect paths for SPI based Serial Engine device
> and vote accordingly based on maximum supported SPI frequency.
>
> Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
> ---
>  drivers/spi/spi-geni-qcom.c | 20 +++++++++++++++++++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> index fdb7cb88..7bbbe9d 100644
> --- a/drivers/spi/spi-geni-qcom.c
> +++ b/drivers/spi/spi-geni-qcom.c
> @@ -12,6 +12,7 @@
>  #include <linux/qcom-geni-se.h>
>  #include <linux/spi/spi.h>
>  #include <linux/spinlock.h>
> +#include <linux/interconnect.h>

Sorted includes please, as mentioned by others.

>
>  /* SPI SE specific registers and respective register fields */
>  #define SE_SPI_CPHA            0x224
> @@ -589,6 +590,15 @@ static int spi_geni_probe(struct platform_device *pdev)
>         spin_lock_init(&mas->lock);
>         pm_runtime_enable(&pdev->dev);
>
> +       /* Set the bus quota to a reasonable value */
> +       mas->se.avg_bw = Bps_to_icc(2500);
> +       mas->se.peak_bw = Bps_to_icc(200000000);

Like the i2c case, can we compute real value based on clock speed?

Patch
diff mbox series

diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index fdb7cb88..7bbbe9d 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -12,6 +12,7 @@ 
 #include <linux/qcom-geni-se.h>
 #include <linux/spi/spi.h>
 #include <linux/spinlock.h>
+#include <linux/interconnect.h>
 
 /* SPI SE specific registers and respective register fields */
 #define SE_SPI_CPHA		0x224
@@ -589,6 +590,15 @@  static int spi_geni_probe(struct platform_device *pdev)
 	spin_lock_init(&mas->lock);
 	pm_runtime_enable(&pdev->dev);
 
+	/* Set the bus quota to a reasonable value */
+	mas->se.avg_bw = Bps_to_icc(2500);
+	mas->se.peak_bw = Bps_to_icc(200000000);
+	ret = geni_interconnect_init(&mas->se);
+	if (ret) {
+		dev_err(&pdev->dev, "interconnect_init failed %d\n", ret);
+		return ret;
+	}
+
 	ret = spi_geni_init(mas);
 	if (ret)
 		goto spi_geni_probe_runtime_disable;
@@ -628,8 +638,15 @@  static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
 {
 	struct spi_master *spi = dev_get_drvdata(dev);
 	struct spi_geni_master *mas = spi_master_get_devdata(spi);
+	int ret;
 
-	return geni_se_resources_off(&mas->se);
+	ret = geni_se_resources_off(&mas->se);
+	if (ret)
+		return ret;
+
+	geni_icc_update_bw(&mas->se, false);
+
+	return 0;
 }
 
 static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
@@ -637,6 +654,7 @@  static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
 	struct spi_master *spi = dev_get_drvdata(dev);
 	struct spi_geni_master *mas = spi_master_get_devdata(spi);
 
+	geni_icc_update_bw(&mas->se, true);
 	return geni_se_resources_on(&mas->se);
 }