[6/6] arm64: dts: sdm845: Add interconnect for GENI QUP
diff mbox series

Message ID 1548138816-1149-7-git-send-email-alokc@codeaurora.org
State New, archived
Headers show
Series
  • Add interconnect support for GENI QUPs
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Commit Message

Alok Chauhan Jan. 22, 2019, 6:33 a.m. UTC
Add interconnect ports for GENI QUPs to set bus
capabilities.

Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Alok Chauhan Jan. 23, 2019, 6:54 a.m. UTC | #1
+Mark Brown

On 2019-01-22 12:03, Alok Chauhan wrote:
> Add interconnect ports for GENI QUPs to set bus
> capabilities.
> 
> Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index c27cbd3..fb0a8a7 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -374,6 +374,13 @@
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> +
> +			interconnects = <&rsc_hlos MASTER_BLSP_1
> +					&rsc_hlos SLAVE_EBI1>,
> +					<&rsc_hlos MASTER_APPSS_PROC
> +					&rsc_hlos SLAVE_BLSP_1>;
> +			interconnect-names = "qup-memory", "qup-config";
> +
>  			status = "disabled";
> 
>  			i2c0: i2c@880000 {
> @@ -682,6 +689,13 @@
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> +
> +			interconnects = <&rsc_hlos MASTER_BLSP_2
> +					&rsc_hlos SLAVE_EBI1>,
> +					<&rsc_hlos MASTER_APPSS_PROC
> +					&rsc_hlos SLAVE_BLSP_2>;
> +			interconnect-names = "qup-memory", "qup-config";
> +
>  			status = "disabled";
> 
>  			i2c8: i2c@a80000 {

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index c27cbd3..fb0a8a7 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -374,6 +374,13 @@ 
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
+
+			interconnects = <&rsc_hlos MASTER_BLSP_1
+					&rsc_hlos SLAVE_EBI1>,
+					<&rsc_hlos MASTER_APPSS_PROC
+					&rsc_hlos SLAVE_BLSP_1>;
+			interconnect-names = "qup-memory", "qup-config";
+
 			status = "disabled";
 
 			i2c0: i2c@880000 {
@@ -682,6 +689,13 @@ 
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
+
+			interconnects = <&rsc_hlos MASTER_BLSP_2
+					&rsc_hlos SLAVE_EBI1>,
+					<&rsc_hlos MASTER_APPSS_PROC
+					&rsc_hlos SLAVE_BLSP_2>;
+			interconnect-names = "qup-memory", "qup-config";
+
 			status = "disabled";
 
 			i2c8: i2c@a80000 {