| Message ID | 20190124185936.27709-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | None | expand |
On Thu, Jan 24, 2019 at 08:59:36PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > With gtt remapping plugged in we can simply raise the stride > limit on gen4+. Let's just pick the limit to match the render > engine max stride (256KiB). > > No remapping CCS because the virtual address of each page actually > matters due to the new hash mode > (WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no > remapping on gen2/3 due extra complications from fence alignment > and gen2 2KiB GTT tile size. Also no real benefit since the > display engine limits already match the other limits. > > v2: Rebase due to is_ccs_modifier() > v3: Tweak the comment and commit msg > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > drivers/gpu/drm/i915/intel_display.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 3713b6f1796e..e0cf43336b62 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2470,6 +2470,15 @@ static > u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, > u32 pixel_format, u64 modifier) > { > + /* > + * Arbitrary limit for gen4+ chosen to match the > + * render engine max stride. > + * > + * The new CCS hash mode makes remapping impossible > + */ > + if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier)) > + return 256*1024; bikeshed: KB(256) but I'm not sure how much we use these really. -Daniel > + > return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); > } > > -- > 2.19.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Daniel Vetter (2019-01-30 09:58:56) > On Thu, Jan 24, 2019 at 08:59:36PM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > With gtt remapping plugged in we can simply raise the stride > > limit on gen4+. Let's just pick the limit to match the render > > engine max stride (256KiB). > > > > No remapping CCS because the virtual address of each page actually > > matters due to the new hash mode > > (WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no > > remapping on gen2/3 due extra complications from fence alignment > > and gen2 2KiB GTT tile size. Also no real benefit since the > > display engine limits already match the other limits. > > > > v2: Rebase due to is_ccs_modifier() > > v3: Tweak the comment and commit msg > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> > > > --- > > drivers/gpu/drm/i915/intel_display.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 3713b6f1796e..e0cf43336b62 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -2470,6 +2470,15 @@ static > > u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, > > u32 pixel_format, u64 modifier) > > { > > + /* > > + * Arbitrary limit for gen4+ chosen to match the > > + * render engine max stride. > > + * > > + * The new CCS hash mode makes remapping impossible > > + */ > > + if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier)) > > + return 256*1024; > > bikeshed: KB(256) but I'm not sure how much we use these really. Polka-dot bikeshed: SZ_256K -Chris
On Wed, Jan 30, 2019 at 10:01:04AM +0000, Chris Wilson wrote: > Quoting Daniel Vetter (2019-01-30 09:58:56) > > On Thu, Jan 24, 2019 at 08:59:36PM +0200, Ville Syrjala wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > With gtt remapping plugged in we can simply raise the stride > > > limit on gen4+. Let's just pick the limit to match the render > > > engine max stride (256KiB). > > > > > > No remapping CCS because the virtual address of each page actually > > > matters due to the new hash mode > > > (WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no > > > remapping on gen2/3 due extra complications from fence alignment > > > and gen2 2KiB GTT tile size. Also no real benefit since the > > > display engine limits already match the other limits. > > > > > > v2: Rebase due to is_ccs_modifier() > > > v3: Tweak the comment and commit msg > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> > > > > > --- > > > drivers/gpu/drm/i915/intel_display.c | 9 +++++++++ > > > 1 file changed, 9 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > > index 3713b6f1796e..e0cf43336b62 100644 > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > @@ -2470,6 +2470,15 @@ static > > > u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, > > > u32 pixel_format, u64 modifier) > > > { > > > + /* > > > + * Arbitrary limit for gen4+ chosen to match the > > > + * render engine max stride. > > > + * > > > + * The new CCS hash mode makes remapping impossible > > > + */ > > > + if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier)) > > > + return 256*1024; > > > > bikeshed: KB(256) but I'm not sure how much we use these really. > > Polka-dot bikeshed: SZ_256K I tried a cocci conversion to these, but ended up being slightly annoyed by the fact that we only have defines for POT sizes, and there are quite a few non-POT sizes in the code.
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3713b6f1796e..e0cf43336b62 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2470,6 +2470,15 @@ static u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier) { + /* + * Arbitrary limit for gen4+ chosen to match the + * render engine max stride. + * + * The new CCS hash mode makes remapping impossible + */ + if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier)) + return 256*1024; + return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); }