diff mbox series

[RESEND,v2,2/2] ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges

Message ID 20190125095740.31889-2-s.trumtrar@pengutronix.de (mailing list archive)
State Mainlined
Commit 29aed3ef6d4985bf8d3ef6505c3e63efc838414e
Headers show
Series [RESEND,v2,1/2] ARM: dts: socfgpa: set bridges status to disabled | expand

Commit Message

Steffen Trumtrar Jan. 25, 2019, 9:57 a.m. UTC
Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f53d9dd05d28..d0cdc331f125 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -538,6 +538,20 @@ 
 			status = "disabled";
 		};
 
+		fpga_bridge2: fpga-bridge@ff600000 {
+			compatible = "altr,socfpga-fpga2hps-bridge";
+			reg = <0xff600000 0x100000>;
+			resets = <&rst FPGA2HPS_RESET>;
+			clocks = <&l4_main_clk>;
+			status = "disabled";
+		};
+
+		fpga_bridge3: fpga-bridge@ffc25080 {
+			compatible = "altr,socfpga-fpga2sdram-bridge";
+			reg = <0xffc25080 0x4>;
+			status = "disabled";
+		};
+
 		fpgamgr0: fpgamgr@ff706000 {
 			compatible = "altr,socfpga-fpga-mgr";
 			reg = <0xff706000 0x1000