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Hou" X-Patchwork-Id: 10785757 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D4FD41390 for ; Tue, 29 Jan 2019 08:15:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C49062B19E for ; Tue, 29 Jan 2019 08:15:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B89322B2B1; Tue, 29 Jan 2019 08:15:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 075852B19E for ; Tue, 29 Jan 2019 08:15:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Content-ID:In-Reply-To: References:Message-ID:Date:Subject:To:From:Reply-To:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aIM2ptR25MyGWmf7FyE6FuSDXNfL0miepIxEf/qGazg=; b=sT7CF6MvTiyblN N6oNLTZ8Y1bboT5fob8LjO+X19oxfXg0/4KY+cmzcW0uxE80C9hD6V31uVgaSJavVEdttR/BPq5KC KSrq4tVwAHupXpufZl3ajfueXJGH0mdErGOKefwH970vLXw0WuE6wexjLls78xdT8xYexH9kskseh 73St81W7WaJTxYReEA7WThQIXC9NbDKsEFnQbY/OvyoZbt2J3YItcUf8x7V3ZAjrAM3LRpnD0AcQA XuBORTB432207UpzcCaCAGKN/SqwIUa5RiLBdwz10WYY7eY6WW+IfLTNNcuwpBwgeWedFpjOmM+EY PUF2fxPdrk0EYZc33EXg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1goOYD-00039r-Sp; Tue, 29 Jan 2019 08:15:21 +0000 Received: from mail-eopbgr60054.outbound.protection.outlook.com ([40.107.6.54] helo=EUR04-DB3-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1goOUP-0007Cv-30 for linux-arm-kernel@lists.infradead.org; Tue, 29 Jan 2019 08:11:59 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=A/Icsp6awN1/HjOv9fcYeOBmIlfKDWu40+XUq47p5F0=; b=DBMj7Hivyk2xp08NPHP1WNhf/oR0a/FIJYTTCe3tiX2oIpu8KHbrw/8MIN65eLzx3+fqXZPXseD8gfKJHDGYCYQg4MU6tbizyK1RrW64JAJjwF2qYge/kA527b8K5Xyu0h73w50M5cv5LTgVCklPYABlreTbtya/xdAeGuZF+jE= Received: from AM6PR04MB5781.eurprd04.prod.outlook.com (20.179.3.19) by AM6PR04MB6117.eurprd04.prod.outlook.com (20.179.7.206) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1580.16; Tue, 29 Jan 2019 08:10:55 +0000 Received: from AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::9c0:e3aa:b41f:9504]) by AM6PR04MB5781.eurprd04.prod.outlook.com ([fe80::9c0:e3aa:b41f:9504%3]) with mapi id 15.20.1558.023; Tue, 29 Jan 2019 08:10:55 +0000 From: "Z.q. Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" Subject: [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Thread-Topic: [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Thread-Index: AQHUt6ooIbohmtKJCU+vMgKKlyN9rQ== Date: Tue, 29 Jan 2019 08:10:55 +0000 Message-ID: <20190129080926.36773-24-Zhiqiang.Hou@nxp.com> References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK0PR04CA0008.apcprd04.prod.outlook.com (2603:1096:203:36::20) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:ad::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR04MB6117; 6:WzRp2WGFrFyDqAXkO5rQJtMcGsVGDy9j/WxK+k8zH2B+F5L5dpebNkxRIYncMBgkBfCSkFhIb0h0zPEwNnXQYx607X75LhcNf90t2uX4k2CpPWE5FnWPH29allLyNXJXsmhMBXx36/aKJ+t0KlKC6Nl2ODeH/7bW6Bk5rKeW4rWGeGnpGKbn68wVOJ/+qemon7mlCuw6/mrA/nbw7PZU1sTB+zzNJDJ0f+Nu5Tf+nQyArzQR2ZqyYQmVs+dbW2J2kEUFIji+BO9VX3xrSDtufueqZj6wCcH1NfOnCj891VRm3mpmWS2iR088Iju8fxOjY+A2gztZbOtdOxbJBXrccyPprn6K2Tu0qZ1ASEBmKvPim6UCEQkp4xWWKvooBzPISiUv0XqoxT55gcq6gL55AU3iKaJv+BrO7SPocdIRgFx+IchDqbr5IfKPPQDNAhSjK94mq/Lf92hUFe9a0VeAzA==; 5:rGwjYCj7wumtt2drrVrsgPuJ+mmFn69MwEhVFXaZlVeeflGTgC0pxjVqj99BBRt489w2U6oh3bxyDqOQa/Aed8sP1VZ3s1AMVOSBfR9Q8U0YO7+PwT+NNCKI2TJjJKfBn9zVJ/Gibp4TdnWGdfDj/7/WhieTC3w67OGmfllRgRIq2PPzNFWMwtboB8TzGEh5lfyVgUjmFfIfEBydbtNDBw==; 7:Jz5LIVehabhgsTo8x+bjAZaJZ6QwPEtXdTlv/NbNetrjRH4oVVtJYD0zZF3jlEfmPXxn/P2i9VVhdgE69J3YjrSlxPVu38ev89rm7HXc//JNKCUlRJXmwZ2bfR7RF5bjT1isiqwlMwPjnpK/HNh6Mg== x-ms-office365-filtering-correlation-id: c90f7b6c-d69f-4e0e-1dff-08d685c14ad6 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600110)(711020)(4605077)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM6PR04MB6117; x-ms-traffictypediagnostic: AM6PR04MB6117: x-microsoft-antispam-prvs: x-forefront-prvs: 093290AD39 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6029001)(396003)(366004)(346002)(376002)(39860400002)(136003)(199004)(189003)(3846002)(6116002)(486006)(81166006)(81156014)(8676002)(7416002)(106356001)(14454004)(478600001)(386003)(446003)(11346002)(186003)(102836004)(476003)(6506007)(8936002)(50226002)(105586002)(68736007)(71190400001)(2906002)(2616005)(71200400001)(36756003)(2501003)(66066001)(97736004)(26005)(4326008)(25786009)(6436002)(6486002)(53936002)(6512007)(256004)(54906003)(7736002)(14444005)(99286004)(305945005)(76176011)(2201001)(110136005)(1076003)(316002)(86362001)(52116002)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB6117; H:AM6PR04MB5781.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: j4G4b9LE3+3VBvtflb4uruKCf93RnEuxczKa4XnHRwD2+DCv9zJ9J32X7MUv4j+3OBDIyV/A6fwBcXfMLf1eN0gsHc9uaUYeEhFBWkVDouHEmJLBHB5WV6py8psXgGWvuEcLZ9alQZiZkC0O4u3fIZSllfdTqnHwxRMI+J+eD49kk/0wTfLOtfRlRFTyoJUUmfwb2ctwJ9I6eHJzO6SUfcwTCygtMrVEaA0ZucygO265m6V7ZhtLlU+lAX0ZpOw4pB0mX3mv/JcZiUSTQwpTa3NUmv3DL7KpjsBdESC/UsbbBoAcjBJ+0ccG/hmeiqHFp9oXZs6byEcGyV9Ihp2SkXJQ74A4OiOL5VvY25w5lTnaFKRDWgETSPlJ3t8Vyp9Bh9+M8qFsIYZlrE5HTCkU3tTh2S8D64C95vBzW/aDi+U= Content-ID: MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c90f7b6c-d69f-4e0e-1dff-08d685c14ad6 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Jan 2019 08:10:49.3981 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB6117 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190129_001126_093469_36D055FC X-CRM114-Status: GOOD ( 18.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "M.h. Lian" , "Z.q. Hou" , Xiaowei Bao , Mingkai Hu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Hou Zhiqiang This PCIe controller is based on the Mobiveil GPEX IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang Reviewed-by: Minghuan Lian --- V3: - No change drivers/pci/controller/mobiveil/Kconfig | 10 + drivers/pci/controller/mobiveil/Makefile | 1 + .../controller/mobiveil/pci-layerscape-gen4.c | 254 ++++++++++++++++++ .../pci/controller/mobiveil/pcie-mobiveil.h | 16 +- 4 files changed, 279 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/controller/mobiveil/pci-layerscape-gen4.c diff --git a/drivers/pci/controller/mobiveil/Kconfig b/drivers/pci/controller/mobiveil/Kconfig index 64343c07bfed..3ddb7d6163a9 100644 --- a/drivers/pci/controller/mobiveil/Kconfig +++ b/drivers/pci/controller/mobiveil/Kconfig @@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT Soft IP. It has up to 8 outbound and inbound windows for address translation and it is a PCIe Gen4 IP. +config PCI_LAYERSCAPE_GEN4 + bool "Freescale Layerscpe PCIe Gen4 controller" + depends on PCI + depends on OF && (ARM64 || ARCH_LAYERSCAPE) + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_MOBIVEIL_HOST + help + Say Y here if you want PCIe Gen4 controller support on + Layerscape SoCs. The PCIe controller can work in RC or + EP mode according to RCW[HOST_AGT_PEX] setting. endmenu diff --git a/drivers/pci/controller/mobiveil/Makefile b/drivers/pci/controller/mobiveil/Makefile index 9fb6d1c6504d..ff66774ccac4 100644 --- a/drivers/pci/controller/mobiveil/Makefile +++ b/drivers/pci/controller/mobiveil/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c new file mode 100644 index 000000000000..174cbcac4059 --- /dev/null +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for NXP Layerscape SoCs + * + * Copyright 2018 NXP + * + * Author: Zhiqiang Hou + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-mobiveil.h" + +/* LUT and PF control registers */ +#define PCIE_LUT_OFF (0x80000) +#define PCIE_PF_OFF (0xc0000) +#define PCIE_PF_INT_STAT (0x18) +#define PF_INT_STAT_PABRST (31) + +#define PCIE_PF_DBG (0x7fc) +#define PF_DBG_LTSSM_MASK (0x3f) +#define PF_DBG_WE (31) +#define PF_DBG_PABR (27) + +#define LS_PCIE_G4_LTSSM_L0 0x2d /* L0 state */ + +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev) + +struct ls_pcie_g4 { + struct mobiveil_pcie *pci; + struct delayed_work dwork; + int irq; +}; + +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) +{ + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off); +} + +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie, + u32 off, u32 val) +{ + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off); +} + +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) +{ + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off); +} + +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, + u32 off, u32 val) +{ + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off); +} + +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = pcie->pci; + u32 header_type; + + header_type = csr_readb(mv_pci, PCI_HEADER_TYPE); + header_type &= 0x7f; + + return header_type == PCI_HEADER_TYPE_BRIDGE; +} + +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) +{ + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); + u32 state; + + state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + state = state & PF_DBG_LTSSM_MASK; + + if (state == LS_PCIE_G4_LTSSM_L0) + return 1; + + return 0; +} + +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = pcie->pci; + u32 val, act_stat; + int to = 100; + + /* Poll for pab_csb_reset to set and PAB activity to clear */ + do { + usleep_range(10, 15); + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT); + act_stat = csr_readl(mv_pci, PAB_ACTIVITY_STAT); + } while (((val & 1 << PF_INT_STAT_PABRST) == 0 || act_stat) && to--); + if (to < 0) { + dev_err(&mv_pci->pdev->dev, "poll PABRST&PABACT timeout\n"); + return; + } + + /* clear PEX_RESET bit in PEX_PF0_DBG register */ + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val |= 1 << PF_DBG_WE; + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val |= 1 << PF_DBG_PABR; + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); + val &= ~(1 << PF_DBG_WE); + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); + + mobiveil_host_init(mv_pci, true); + + to = 100; + while (!ls_pcie_g4_link_up(mv_pci) && to--) + usleep_range(200, 250); + if (to < 0) + dev_err(&mv_pci->pdev->dev, "PCIe link trainning timeout\n"); +} + +static irqreturn_t ls_pcie_g4_handler(int irq, void *dev_id) +{ + struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id; + struct mobiveil_pcie *mv_pci = pcie->pci; + u32 val; + + val = csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT); + if (!val) + return IRQ_NONE; + + if (val & PAB_INTP_RESET) + schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1)); + + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT); + + return IRQ_HANDLED; +} + +static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci) +{ + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci); + u32 val; + int ret; + + pcie->irq = platform_get_irq_byname(mv_pci->pdev, "intr"); + if (pcie->irq < 0) { + dev_err(&mv_pci->pdev->dev, "Can't get 'intr' irq.\n"); + return pcie->irq; + } + ret = devm_request_irq(&mv_pci->pdev->dev, pcie->irq, + ls_pcie_g4_handler, IRQF_SHARED, + mv_pci->pdev->name, pcie); + if (ret) { + dev_err(&mv_pci->pdev->dev, "Can't register PCIe IRQ.\n"); + return ret; + } + + /* Enable interrupts */ + val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET | + PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC; + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB); + + return 0; +} + +static void ls_pcie_g4_reset(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work, struct delayed_work, + work); + struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork); + struct mobiveil_pcie *mv_pci = pcie->pci; + u16 ctrl; + + ctrl = csr_readw(mv_pci, PCI_BRIDGE_CONTROL); + ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; + csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL); + ls_pcie_g4_reinit_hw(pcie); +} + +static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = { + .interrupt_init = ls_pcie_g4_interrupt_init, +}; + +static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = { + .link_up = ls_pcie_g4_link_up, +}; + +static int __init ls_pcie_g4_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mobiveil_pcie *mv_pci; + struct ls_pcie_g4 *pcie; + struct device_node *np = dev->of_node; + int ret; + + if (!of_parse_phandle(np, "msi-parent", 0)) { + dev_err(dev, "failed to find msi-parent\n"); + return -EINVAL; + } + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL); + if (!mv_pci) + return -ENOMEM; + + mv_pci->pdev = pdev; + mv_pci->ops = &ls_pcie_g4_pab_ops; + mv_pci->rp.ops = &ls_pcie_g4_rp_ops; + pcie->pci = mv_pci; + + platform_set_drvdata(pdev, pcie); + + INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset); + + ret = mobiveil_pcie_host_probe(mv_pci); + if (ret) { + dev_err(dev, "fail to probe!\n"); + return ret; + } + + if (!ls_pcie_g4_is_bridge(pcie)) + return -ENODEV; + + return 0; +} + +static const struct of_device_id ls_pcie_g4_of_match[] = { + { .compatible = "fsl,lx2160a-pcie", }, + { }, +}; + +static struct platform_driver ls_pcie_g4_driver = { + .driver = { + .name = "layerscape-pcie-gen4", + .of_match_table = ls_pcie_g4_of_match, + .suppress_bind_attrs = true, + }, +}; + +builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h index 0f5303962e88..0ccd6cee5f8f 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -41,6 +41,8 @@ #define PAGE_LO_MASK 0x3ff #define PAGE_SEL_OFFSET_SHIFT 10 +#define PAB_ACTIVITY_STAT 0x81c + #define PAB_AXI_PIO_CTRL 0x0840 #define APIO_EN_MASK 0xf @@ -49,8 +51,18 @@ #define PAB_INTP_AMBA_MISC_ENB 0x0b0c #define PAB_INTP_AMBA_MISC_STAT 0x0b1c -#define PAB_INTP_INTX_MASK 0x01e0 -#define PAB_INTP_MSI_MASK 0x8 +#define PAB_INTP_RESET (0x1 << 1) +#define PAB_INTP_MSI (0x1 << 3) +#define PAB_INTP_INTA (0x1 << 5) +#define PAB_INTP_INTB (0x1 << 6) +#define PAB_INTP_INTC (0x1 << 7) +#define PAB_INTP_INTD (0x1 << 8) +#define PAB_INTP_PCIE_UE (0x1 << 9) +#define PAB_INTP_IE_PMREDI (0x1 << 29) +#define PAB_INTP_IE_EC (0x1 << 30) +#define PAB_INTP_MSI_MASK PAB_INTP_MSI +#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\ + PAB_INTP_INTC | PAB_INTP_INTD) #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) #define WIN_ENABLE_SHIFT 0