[v4,2/2] spi-atmel: support inter-word delay
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Message ID 20190129083844.20572-3-jonas@norrbonn.se
State New, archived
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Series
  • [v4,1/2] spi: support inter-word delay requirement for devices
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Commit Message

Jonas Bonn Jan. 29, 2019, 8:38 a.m. UTC
If the SPI slave requires an inter-word delay, configure the DLYBCT
register accordingly.

Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
board).

Signed-off-by: Jonas Bonn <jonas@norrbonn.se>
CC: Nicolas Ferre <nicolas.ferre@microchip.com>
CC: Mark Brown <broonie@kernel.org>
CC: Alexandre Belloni <alexandre.belloni@bootlin.com>
CC: Ludovic Desroches <ludovic.desroches@microchip.com>
CC: linux-spi@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
---
 drivers/spi/spi-atmel.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

Comments

Nicolas Ferre Jan. 29, 2019, 2:27 p.m. UTC | #1
On 29/01/2019 at 09:38, Jonas Bonn wrote:
> If the SPI slave requires an inter-word delay, configure the DLYBCT
> register accordingly.
> 
> Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
> board).
> 
> Signed-off-by: Jonas Bonn <jonas@norrbonn.se>
> CC: Nicolas Ferre <nicolas.ferre@microchip.com>
> CC: Mark Brown <broonie@kernel.org>
> CC: Alexandre Belloni <alexandre.belloni@bootlin.com>
> CC: Ludovic Desroches <ludovic.desroches@microchip.com>
> CC: linux-spi@vger.kernel.org
> CC: linux-arm-kernel@lists.infradead.org
> ---
>   drivers/spi/spi-atmel.c | 18 +++++++++++++-----
>   1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 74fddcd3282b..6389a228d2f5 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -1209,13 +1209,21 @@ static int atmel_spi_setup(struct spi_device *spi)
>   		csr |= SPI_BIT(CSAAT);
>   
>   	/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
> -	 *
> -	 * DLYBCT would add delays between words, slowing down transfers.
> -	 * It could potentially be useful to cope with DMA bottlenecks, but
> -	 * in those cases it's probably best to just use a lower bitrate.
>   	 */
>   	csr |= SPI_BF(DLYBS, 0);
> -	csr |= SPI_BF(DLYBCT, 0);
> +
> +	/* DLYBCT adds delays between words.  This is useful for slow devices
> +	 * that need a bit of time to setup the next transfer.
> +	 */
> +	if (spi->word_delay_us) {

Well...

> +		csr |= SPI_BF(DLYBCT,
> +			clamp_t(u8,
> +				(as->spi_clk/1000000*spi->word_delay_us)>>5,
> +				1, 255));

... why not simplifying to:
+				0, 255));
and remove the test altogether, after all?

> +	} else {
> +		csr |= SPI_BF(DLYBCT, 0);
> +	}
> +
>   
>   	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
>   	npcs_pin = (unsigned long)spi->controller_data;
>
Jonas Bonn Jan. 29, 2019, 2:56 p.m. UTC | #2
Hi,

On 29/01/2019 15:27, Nicolas.Ferre@microchip.com wrote:
> On 29/01/2019 at 09:38, Jonas Bonn wrote:
>> 
>> +	/* DLYBCT adds delays between words.  This is useful for slow devices
>> +	 * that need a bit of time to setup the next transfer.
>> +	 */
>> +	if (spi->word_delay_us) {
> 
> Well...
> 
>> +		csr |= SPI_BF(DLYBCT,
>> +			clamp_t(u8,
>> +				(as->spi_clk/1000000*spi->word_delay_us)>>5,
>> +				1, 255));
> 
> ... why not simplifying to:
> +				0, 255));
> and remove the test altogether, after all?

Hmm... that seemed too easy!  This started out as something else and 
looking at it now I think even the clamp_t() is unnecessary.  The value 
is already 0-255 and the way SPI_BF works any overflow is already 
truncated...  I'll rework this and resubmit once I get some feedback on 
the word_delay_us bits.

Thanks,
/Jonas
Alexandre Belloni Jan. 29, 2019, 3:05 p.m. UTC | #3
Hi,

On 29/01/2019 15:56:31+0100, Jonas Bonn wrote:
> On 29/01/2019 15:27, Nicolas.Ferre@microchip.com wrote:
> > On 29/01/2019 at 09:38, Jonas Bonn wrote:
> > > 
> > > +	/* DLYBCT adds delays between words.  This is useful for slow devices
> > > +	 * that need a bit of time to setup the next transfer.
> > > +	 */
> > > +	if (spi->word_delay_us) {
> > 
> > Well...
> > 
> > > +		csr |= SPI_BF(DLYBCT,
> > > +			clamp_t(u8,
> > > +				(as->spi_clk/1000000*spi->word_delay_us)>>5,
> > > +				1, 255));
> > 
> > ... why not simplifying to:
> > +				0, 255));
> > and remove the test altogether, after all?
> 
> Hmm... that seemed too easy!  This started out as something else and looking
> at it now I think even the clamp_t() is unnecessary.  The value is already
> 0-255 and the way SPI_BF works any overflow is already truncated...  I'll
> rework this and resubmit once I get some feedback on the word_delay_us bits.
> 

While at it, note that you need to add spaces around the operators.

Patch
diff mbox series

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 74fddcd3282b..6389a228d2f5 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -1209,13 +1209,21 @@  static int atmel_spi_setup(struct spi_device *spi)
 		csr |= SPI_BIT(CSAAT);
 
 	/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
-	 *
-	 * DLYBCT would add delays between words, slowing down transfers.
-	 * It could potentially be useful to cope with DMA bottlenecks, but
-	 * in those cases it's probably best to just use a lower bitrate.
 	 */
 	csr |= SPI_BF(DLYBS, 0);
-	csr |= SPI_BF(DLYBCT, 0);
+
+	/* DLYBCT adds delays between words.  This is useful for slow devices
+	 * that need a bit of time to setup the next transfer.
+	 */
+	if (spi->word_delay_us) {
+		csr |= SPI_BF(DLYBCT,
+			clamp_t(u8,
+				(as->spi_clk/1000000*spi->word_delay_us)>>5,
+				1, 255));
+	} else {
+		csr |= SPI_BF(DLYBCT, 0);
+	}
+
 
 	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
 	npcs_pin = (unsigned long)spi->controller_data;