ARM: socfpga: fix base address of SDR controller
diff mbox series

Message ID 20190129200858.19773-1-goldsimon@gmx.de
State New
Headers show
Series
  • ARM: socfpga: fix base address of SDR controller
Related show

Commit Message

Simon Goldschmidt Jan. 29, 2019, 8:08 p.m. UTC
From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

The documentation for socfpga gen5 says the base address of the sdram
controller is 0xffc20000, while the current devicetree says it is at
0xffc25000.

While this is not a problem for Linux, as it only accesses the registers
above 0xffc25000, it *is* a problem for U-Boot because the lower registers
are used during DDR calibration (up to now, the U-Boot driver does not use
the dts address, but that should change).

To keep Linux and U-Boot devicetrees in sync, this patch changes the base
address to 0xffc20000 and adapts the 2 files where it is currently used.

This patch changes the dts and 2 drivers with one commit to prevent
breaking the code if dts change and driver change would be split.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

 arch/arm/boot/dts/socfpga.dtsi       | 4 ++--
 arch/arm/mach-socfpga/self-refresh.S | 4 ++--
 drivers/fpga/altera-fpga2sdram.c     | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

Comments

Alan Tull Jan. 29, 2019, 10:30 p.m. UTC | #1
On Tue, Jan 29, 2019 at 2:09 PM Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:

Hi Simon,

Thanks for submitting.   A couple of things...

> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index f365003f0..8f6c1a5d6 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -788,9 +788,9 @@
>                         reg = <0xfffec000 0x100>;
>                 };
>
> -               sdr: sdr@ffc25000 {
> +               sdr: sdr@ffc20000 {
>                         compatible = "altr,sdr-ctl", "syscon";
> -                       reg = <0xffc25000 0x1000>;
> +                       reg = <0xffc20000 0x6000>;

The binding doc will also need this change (in a separate patch)
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt

> diff --git a/arch/arm/mach-socfpga/self-refresh.S b/arch/arm/mach-socfpga/self-refresh.S
> index f2d7f883e..bd7759357 100644
> --- a/arch/arm/mach-socfpga/self-refresh.S
> +++ b/arch/arm/mach-socfpga/self-refresh.S
> @@ -19,8 +19,8 @@
>  #define MAX_LOOP_COUNT         1000
>
>  /* Register offset */
> -#define SDR_CTRLGRP_LOWPWREQ_ADDR       0x54
> -#define SDR_CTRLGRP_LOWPWRACK_ADDR      0x58
> +#define SDR_CTRLGRP_LOWPWREQ_ADDR       0x5054
> +#define SDR_CTRLGRP_LOWPWRACK_ADDR      0x5058

These offsets are used for ldr/sdr and are limited to 12 bits.  This
won't build if CONFIG_SOCFPGA_SUSPEND is enabled.

/home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:
Assembler messages:
/home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:65:
Error: bad immediate value for offset (20564)
/home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:67:
Error: bad immediate value for offset (20564)
/home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:72:
Error: bad immediate value for offset (20568)
/home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:101:
Error: bad immediate value for offset (20564)
/home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:103:
Error: bad immediate value for offset (20564)
/home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:108:
Error: bad immediate value for offset (20568)
/home/atull/repos/linux-socfpga/scripts/Makefile.build:367: recipe for
target 'arch/arm/mach-socfpga/self-refresh.o' failed

Thanks,
Alan
Dinh Nguyen Jan. 30, 2019, 12:16 a.m. UTC | #2
On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
> From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> 
> The documentation for socfpga gen5 says the base address of the sdram
> controller is 0xffc20000, while the current devicetree says it is at
> 0xffc25000.
> 
> While this is not a problem for Linux, as it only accesses the registers
> above 0xffc25000, it *is* a problem for U-Boot because the lower registers
> are used during DDR calibration (up to now, the U-Boot driver does not use
> the dts address, but that should change).
> 
> To keep Linux and U-Boot devicetrees in sync, this patch changes the base
> address to 0xffc20000 and adapts the 2 files where it is currently used.
> 
> This patch changes the dts and 2 drivers with one commit to prevent
> breaking the code if dts change and driver change would be split.
> 
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
> 
>  arch/arm/boot/dts/socfpga.dtsi       | 4 ++--
>  arch/arm/mach-socfpga/self-refresh.S | 4 ++--
>  drivers/fpga/altera-fpga2sdram.c     | 2 +-
>  3 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index f365003f0..8f6c1a5d6 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -788,9 +788,9 @@
>  			reg = <0xfffec000 0x100>;
>  		};
>  
> -		sdr: sdr@ffc25000 {
> +		sdr: sdr@ffc20000 {
>  			compatible = "altr,sdr-ctl", "syscon";
> -			reg = <0xffc25000 0x1000>;
> +			reg = <0xffc20000 0x6000>;

I don't see the U-Boot device tree having this change. Yes, the
documentation does state that the SDR address starts at 0xffc20000, but
all of the pertinent registers start at 0x5000 offset. Thus, the
starting address should be 0xffc25000.[1]

[1]
https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html#sfo1411577366917

Dinh
Simon Goldschmidt Jan. 30, 2019, 6 a.m. UTC | #3
+ Marek (as I really want to keep the dts in Linux and U-Boot in sync)
On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
>
>
>
> On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
> > From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> >
> > The documentation for socfpga gen5 says the base address of the sdram
> > controller is 0xffc20000, while the current devicetree says it is at
> > 0xffc25000.
> >
> > While this is not a problem for Linux, as it only accesses the registers
> > above 0xffc25000, it *is* a problem for U-Boot because the lower registers
> > are used during DDR calibration (up to now, the U-Boot driver does not use
> > the dts address, but that should change).
> >
> > To keep Linux and U-Boot devicetrees in sync, this patch changes the base
> > address to 0xffc20000 and adapts the 2 files where it is currently used.
> >
> > This patch changes the dts and 2 drivers with one commit to prevent
> > breaking the code if dts change and driver change would be split.
> >
> > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> > ---
> >
> >  arch/arm/boot/dts/socfpga.dtsi       | 4 ++--
> >  arch/arm/mach-socfpga/self-refresh.S | 4 ++--
> >  drivers/fpga/altera-fpga2sdram.c     | 2 +-
> >  3 files changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index f365003f0..8f6c1a5d6 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -788,9 +788,9 @@
> >                       reg = <0xfffec000 0x100>;
> >               };
> >
> > -             sdr: sdr@ffc25000 {
> > +             sdr: sdr@ffc20000 {
> >                       compatible = "altr,sdr-ctl", "syscon";
> > -                     reg = <0xffc25000 0x1000>;
> > +                     reg = <0xffc20000 0x6000>;
>
> I don't see the U-Boot device tree having this change. Yes, the
> documentation does state that the SDR address starts at 0xffc20000, but
> all of the pertinent registers start at 0x5000 offset. Thus, the
> starting address should be 0xffc25000.[1]

You don't see it in U-Boot as I'm working on a patch for that.
As I wrote in the commit message, U-Boot currently does not use the
devicetree for the SDR driver, but I want to convert it to do that.

But before converting, I need to find a clean way to provide the
register addresses to the driver. That doesn't work with the current dts.

>
> [1]
> https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html#sfo1411577366917

Well, in [2], you see that the peripheral's address range actually starts
at 0xffc20000. It's only the public documented registers that start at
0xffc25000. I don't know why the lower address range is undocumented.
Maybe you can help me here?

But U-Boot needs to use the undocumented registers to bring up the DDR-RAM.
Even if the registers for that are not (clearly?) documented, I think the
devicetree should still reflect the correct address range.

The U-Boot driver is made up of 2 files (in drivers/ddr/altera):
- sdram_gen5.c [3]: using the documented registers from 0xffc25000
- sequencer.c [4]: using the (undocumented?) registers from 0xffc20000

In both files, you can see the register addresses they use by checking the
static variables at the top of the file. And for convenience, use [5] to
search for the values of defines.

[2]
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html
[3]
https://github.com/u-boot/u-boot/blob/master/drivers/ddr/altera/sdram_gen5.c
[4]
https://github.com/u-boot/u-boot/blob/master/drivers/ddr/altera/sequencer.c
[5]
https://elixir.bootlin.com/u-boot/latest/source

Regards,
Simon
Simon Goldschmidt Jan. 30, 2019, 6:08 a.m. UTC | #4
On Tue, Jan 29, 2019 at 11:31 PM Alan Tull <atull@kernel.org> wrote:
>
> On Tue, Jan 29, 2019 at 2:09 PM Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com> wrote:
>
> Hi Simon,
>
> Thanks for submitting.   A couple of things...
>
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index f365003f0..8f6c1a5d6 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -788,9 +788,9 @@
> >                         reg = <0xfffec000 0x100>;
> >                 };
> >
> > -               sdr: sdr@ffc25000 {
> > +               sdr: sdr@ffc20000 {
> >                         compatible = "altr,sdr-ctl", "syscon";
> > -                       reg = <0xffc25000 0x1000>;
> > +                       reg = <0xffc20000 0x6000>;
>
> The binding doc will also need this change (in a separate patch)
> Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt

Right. I didn't realise there is an actual address in that file as it says
"Example"...

But I'll make sure to change that if this patch is accepted.

>
> > diff --git a/arch/arm/mach-socfpga/self-refresh.S b/arch/arm/mach-socfpga/self-refresh.S
> > index f2d7f883e..bd7759357 100644
> > --- a/arch/arm/mach-socfpga/self-refresh.S
> > +++ b/arch/arm/mach-socfpga/self-refresh.S
> > @@ -19,8 +19,8 @@
> >  #define MAX_LOOP_COUNT         1000
> >
> >  /* Register offset */
> > -#define SDR_CTRLGRP_LOWPWREQ_ADDR       0x54
> > -#define SDR_CTRLGRP_LOWPWRACK_ADDR      0x58
> > +#define SDR_CTRLGRP_LOWPWREQ_ADDR       0x5054
> > +#define SDR_CTRLGRP_LOWPWRACK_ADDR      0x5058
>
> These offsets are used for ldr/sdr and are limited to 12 bits.  This
> won't build if CONFIG_SOCFPGA_SUSPEND is enabled.
>
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:
> Assembler messages:
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:65:
> Error: bad immediate value for offset (20564)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:67:
> Error: bad immediate value for offset (20564)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:72:
> Error: bad immediate value for offset (20568)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:101:
> Error: bad immediate value for offset (20564)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:103:
> Error: bad immediate value for offset (20564)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:108:
> Error: bad immediate value for offset (20568)
> /home/atull/repos/linux-socfpga/scripts/Makefile.build:367: recipe for
> target 'arch/arm/mach-socfpga/self-refresh.o' failed

Oops, you're right. Sorry for that. I just saw now that socfpga_defconfig
leaves CONFIG_SOCFPGA_SUSPEND inactive. I'll make sure to test that if it
comes to v2 (depending on the discussion).

Thanks,
Simon
Dinh Nguyen Jan. 30, 2019, 3:50 p.m. UTC | #5
On 1/30/19 12:00 AM, Simon Goldschmidt wrote:
> + Marek (as I really want to keep the dts in Linux and U-Boot in sync)
> On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
>>
>>
>>
>> On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
>>> From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>>
>>> The documentation for socfpga gen5 says the base address of the sdram
>>> controller is 0xffc20000, while the current devicetree says it is at
>>> 0xffc25000.
>>>
>>> While this is not a problem for Linux, as it only accesses the registers
>>> above 0xffc25000, it *is* a problem for U-Boot because the lower registers
>>> are used during DDR calibration (up to now, the U-Boot driver does not use
>>> the dts address, but that should change).
>>>
>>> To keep Linux and U-Boot devicetrees in sync, this patch changes the base
>>> address to 0xffc20000 and adapts the 2 files where it is currently used.
>>>
>>> This patch changes the dts and 2 drivers with one commit to prevent
>>> breaking the code if dts change and driver change would be split.
>>>
>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>> ---
>>>
>>>  arch/arm/boot/dts/socfpga.dtsi       | 4 ++--
>>>  arch/arm/mach-socfpga/self-refresh.S | 4 ++--
>>>  drivers/fpga/altera-fpga2sdram.c     | 2 +-
>>>  3 files changed, 5 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>> index f365003f0..8f6c1a5d6 100644
>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>> @@ -788,9 +788,9 @@
>>>                       reg = <0xfffec000 0x100>;
>>>               };
>>>
>>> -             sdr: sdr@ffc25000 {
>>> +             sdr: sdr@ffc20000 {
>>>                       compatible = "altr,sdr-ctl", "syscon";
>>> -                     reg = <0xffc25000 0x1000>;
>>> +                     reg = <0xffc20000 0x6000>;
>>
>> I don't see the U-Boot device tree having this change. Yes, the
>> documentation does state that the SDR address starts at 0xffc20000, but
>> all of the pertinent registers start at 0x5000 offset. Thus, the
>> starting address should be 0xffc25000.[1]
> 
> You don't see it in U-Boot as I'm working on a patch for that.
> As I wrote in the commit message, U-Boot currently does not use the
> devicetree for the SDR driver, but I want to convert it to do that.

That's great! Can you elaborate on what is the impetus for converting
the SDR driver to use the dts?

Dinh
Simon Goldschmidt Jan. 30, 2019, 4:28 p.m. UTC | #6
Am 30.01.2019 um 16:50 schrieb Dinh Nguyen:
> 
> 
> On 1/30/19 12:00 AM, Simon Goldschmidt wrote:
>> + Marek (as I really want to keep the dts in Linux and U-Boot in sync)
>> On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
>>>
>>>
>>>
>>> On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
>>>> From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>>>
>>>> The documentation for socfpga gen5 says the base address of the sdram
>>>> controller is 0xffc20000, while the current devicetree says it is at
>>>> 0xffc25000.
>>>>
>>>> While this is not a problem for Linux, as it only accesses the registers
>>>> above 0xffc25000, it *is* a problem for U-Boot because the lower registers
>>>> are used during DDR calibration (up to now, the U-Boot driver does not use
>>>> the dts address, but that should change).
>>>>
>>>> To keep Linux and U-Boot devicetrees in sync, this patch changes the base
>>>> address to 0xffc20000 and adapts the 2 files where it is currently used.
>>>>
>>>> This patch changes the dts and 2 drivers with one commit to prevent
>>>> breaking the code if dts change and driver change would be split.
>>>>
>>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>>> ---
>>>>
>>>>   arch/arm/boot/dts/socfpga.dtsi       | 4 ++--
>>>>   arch/arm/mach-socfpga/self-refresh.S | 4 ++--
>>>>   drivers/fpga/altera-fpga2sdram.c     | 2 +-
>>>>   3 files changed, 5 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>>> index f365003f0..8f6c1a5d6 100644
>>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>>> @@ -788,9 +788,9 @@
>>>>                        reg = <0xfffec000 0x100>;
>>>>                };
>>>>
>>>> -             sdr: sdr@ffc25000 {
>>>> +             sdr: sdr@ffc20000 {
>>>>                        compatible = "altr,sdr-ctl", "syscon";
>>>> -                     reg = <0xffc25000 0x1000>;
>>>> +                     reg = <0xffc20000 0x6000>;
>>>
>>> I don't see the U-Boot device tree having this change. Yes, the
>>> documentation does state that the SDR address starts at 0xffc20000, but
>>> all of the pertinent registers start at 0x5000 offset. Thus, the
>>> starting address should be 0xffc25000.[1]
>>
>> You don't see it in U-Boot as I'm working on a patch for that.
>> As I wrote in the commit message, U-Boot currently does not use the
>> devicetree for the SDR driver, but I want to convert it to do that.
> 
> That's great! Can you elaborate on what is the impetus for converting
> the SDR driver to use the dts?

The initial reason to do so was to move its reset handling from U-Boot 
SPL to the driver itself. Moving from ad-hoc code to using the reset driver.

And when it's being converted to using the reset handle from dts, I 
think it should also use the base address from dts.

Regards,
Simon
Dinh Nguyen Feb. 1, 2019, 3:13 p.m. UTC | #7
On 1/30/19 12:00 AM, Simon Goldschmidt wrote:
> + Marek (as I really want to keep the dts in Linux and U-Boot in sync)

So can you wait until your patch in U-Boot is in?

> On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
>>
>>
>>
>> On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
>>> From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>>
>>> The documentation for socfpga gen5 says the base address of the sdram
>>> controller is 0xffc20000, while the current devicetree says it is at
>>> 0xffc25000.
>>>
>>> While this is not a problem for Linux, as it only accesses the registers
>>> above 0xffc25000, it *is* a problem for U-Boot because the lower registers
>>> are used during DDR calibration (up to now, the U-Boot driver does not use
>>> the dts address, but that should change).
>>>
>>> To keep Linux and U-Boot devicetrees in sync, this patch changes the base
>>> address to 0xffc20000 and adapts the 2 files where it is currently used.
>>>
>>> This patch changes the dts and 2 drivers with one commit to prevent
>>> breaking the code if dts change and driver change would be split.
>>>
>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>> ---
>>>
>>>  arch/arm/boot/dts/socfpga.dtsi       | 4 ++--
>>>  arch/arm/mach-socfpga/self-refresh.S | 4 ++--
>>>  drivers/fpga/altera-fpga2sdram.c     | 2 +-
>>>  3 files changed, 5 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>> index f365003f0..8f6c1a5d6 100644
>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>> @@ -788,9 +788,9 @@
>>>                       reg = <0xfffec000 0x100>;
>>>               };
>>>
>>> -             sdr: sdr@ffc25000 {
>>> +             sdr: sdr@ffc20000 {
>>>                       compatible = "altr,sdr-ctl", "syscon";
>>> -                     reg = <0xffc25000 0x1000>;
>>> +                     reg = <0xffc20000 0x6000>;
>>
>> I don't see the U-Boot device tree having this change. Yes, the
>> documentation does state that the SDR address starts at 0xffc20000, but
>> all of the pertinent registers start at 0x5000 offset. Thus, the
>> starting address should be 0xffc25000.[1]
> 
> You don't see it in U-Boot as I'm working on a patch for that.
> As I wrote in the commit message, U-Boot currently does not use the
> devicetree for the SDR driver, but I want to convert it to do that.
> 
> But before converting, I need to find a clean way to provide the
> register addresses to the driver. That doesn't work with the current dts.
> 
>>
>> [1]
>> https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html#sfo1411577366917
> 
> Well, in [2], you see that the peripheral's address range actually starts
> at 0xffc20000. It's only the public documented registers that start at
> 0xffc25000. I don't know why the lower address range is undocumented.
> Maybe you can help me here?
> 

Yes, the reason these register are not documented is that the ddr
engineers didn't really want anyone outside of their team messing around
with the calibration. These registers, from the limited documentation I
have, are related to the PHY settings. I've been told the calibration
sequence is something of a "black" magic.

Dinh
Simon Goldschmidt Feb. 1, 2019, 3:50 p.m. UTC | #8
Am 01.02.2019 um 16:13 schrieb Dinh Nguyen:
> 
> 
> On 1/30/19 12:00 AM, Simon Goldschmidt wrote:
>> + Marek (as I really want to keep the dts in Linux and U-Boot in sync)
> 
> So can you wait until your patch in U-Boot is in?

Well, yes, this could wait. The problem is we wanted to keep Linux and 
U-Boot dts in sync.

I guess I'll just finish preparing my patch for U-Boot changing the dts 
there and then we'll see which part gets pushed first...

> 
>> On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
>>>
>>>
>>>
>>> On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
>>>> From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>>>
>>>> The documentation for socfpga gen5 says the base address of the sdram
>>>> controller is 0xffc20000, while the current devicetree says it is at
>>>> 0xffc25000.
>>>>
>>>> While this is not a problem for Linux, as it only accesses the registers
>>>> above 0xffc25000, it *is* a problem for U-Boot because the lower registers
>>>> are used during DDR calibration (up to now, the U-Boot driver does not use
>>>> the dts address, but that should change).
>>>>
>>>> To keep Linux and U-Boot devicetrees in sync, this patch changes the base
>>>> address to 0xffc20000 and adapts the 2 files where it is currently used.
>>>>
>>>> This patch changes the dts and 2 drivers with one commit to prevent
>>>> breaking the code if dts change and driver change would be split.
>>>>
>>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>>>> ---
>>>>
>>>>   arch/arm/boot/dts/socfpga.dtsi       | 4 ++--
>>>>   arch/arm/mach-socfpga/self-refresh.S | 4 ++--
>>>>   drivers/fpga/altera-fpga2sdram.c     | 2 +-
>>>>   3 files changed, 5 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>>> index f365003f0..8f6c1a5d6 100644
>>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>>> @@ -788,9 +788,9 @@
>>>>                        reg = <0xfffec000 0x100>;
>>>>                };
>>>>
>>>> -             sdr: sdr@ffc25000 {
>>>> +             sdr: sdr@ffc20000 {
>>>>                        compatible = "altr,sdr-ctl", "syscon";
>>>> -                     reg = <0xffc25000 0x1000>;
>>>> +                     reg = <0xffc20000 0x6000>;
>>>
>>> I don't see the U-Boot device tree having this change. Yes, the
>>> documentation does state that the SDR address starts at 0xffc20000, but
>>> all of the pertinent registers start at 0x5000 offset. Thus, the
>>> starting address should be 0xffc25000.[1]
>>
>> You don't see it in U-Boot as I'm working on a patch for that.
>> As I wrote in the commit message, U-Boot currently does not use the
>> devicetree for the SDR driver, but I want to convert it to do that.
>>
>> But before converting, I need to find a clean way to provide the
>> register addresses to the driver. That doesn't work with the current dts.
>>
>>>
>>> [1]
>>> https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html#sfo1411577366917
>>
>> Well, in [2], you see that the peripheral's address range actually starts
>> at 0xffc20000. It's only the public documented registers that start at
>> 0xffc25000. I don't know why the lower address range is undocumented.
>> Maybe you can help me here?
>>
> 
> Yes, the reason these register are not documented is that the ddr
> engineers didn't really want anyone outside of their team messing around
> with the calibration. These registers, from the limited documentation I
> have, are related to the PHY settings. I've been told the calibration
> sequence is something of a "black" magic.

That's exactly how I thought it would be. However, that's not the best 
attitued for getting code into an open source project like U-Boot. For 
example, I wanted to take a look at the code to see if it can be made 
smaller, but that's unnecessary hard if the registers are not documented...

Regards,
Simon

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f365003f0..8f6c1a5d6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -788,9 +788,9 @@ 
 			reg = <0xfffec000 0x100>;
 		};
 
-		sdr: sdr@ffc25000 {
+		sdr: sdr@ffc20000 {
 			compatible = "altr,sdr-ctl", "syscon";
-			reg = <0xffc25000 0x1000>;
+			reg = <0xffc20000 0x6000>;
 		};
 
 		sdramedac {
diff --git a/arch/arm/mach-socfpga/self-refresh.S b/arch/arm/mach-socfpga/self-refresh.S
index f2d7f883e..bd7759357 100644
--- a/arch/arm/mach-socfpga/self-refresh.S
+++ b/arch/arm/mach-socfpga/self-refresh.S
@@ -19,8 +19,8 @@ 
 #define MAX_LOOP_COUNT		1000
 
 /* Register offset */
-#define SDR_CTRLGRP_LOWPWREQ_ADDR       0x54
-#define SDR_CTRLGRP_LOWPWRACK_ADDR      0x58
+#define SDR_CTRLGRP_LOWPWREQ_ADDR       0x5054
+#define SDR_CTRLGRP_LOWPWRACK_ADDR      0x5058
 
 /* Bitfield positions */
 #define SELFRSHREQ_POS                  3
diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera-fpga2sdram.c
index a78e49c63..30767c254 100644
--- a/drivers/fpga/altera-fpga2sdram.c
+++ b/drivers/fpga/altera-fpga2sdram.c
@@ -30,7 +30,7 @@ 
 #include <linux/of_platform.h>
 #include <linux/regmap.h>
 
-#define ALT_SDR_CTL_FPGAPORTRST_OFST		0x80
+#define ALT_SDR_CTL_FPGAPORTRST_OFST		0x5080
 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK	0x00003fff
 #define ALT_SDR_CTL_FPGAPORTRST_RD_SHIFT	0
 #define ALT_SDR_CTL_FPGAPORTRST_WR_SHIFT	4