From patchwork Sun Feb 3 15:56:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 10794753 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C6FEB922 for ; Sun, 3 Feb 2019 15:57:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B4B1E2880F for ; Sun, 3 Feb 2019 15:57:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A714428FD1; Sun, 3 Feb 2019 15:57:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5A7A42880F for ; Sun, 3 Feb 2019 15:57:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lMLau/vAK+VqCj+EbhC2X4dxOkFyhbXpggLwfiku7us=; b=mrl9JobCtP0Sfo YmJFy4FCn1aXrpTdfKoSO4T21Kz/WhSu2uOV8HMhehOiMEJlVBvBO3LOTeaJGKOcHdPHgIMMPyUxA IZRVLsjJS0/jWsIzRzFH3Qg5kEPcGZw75ODNQ0o9oqOMqOqC5GtHUOq1kUYUlFr/f5JsXX3mGNP8d dPDOyWZA9Qqb46DDCUsgjT4XYsNyRdG8CVICeY7rb3/wzaBtoKd8jNOpAsFNUnsjAXE/7Y6N6gROO rEulEHyOYCXEkNPenJAtxOFdKpN/j5Y2u3t5b/IRsJTt7bnIXUjk72GguHRQ6U639ihYtBeLMAQCc vSg99rntmTwvh9YZMS8A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gqK8q-0001O9-Rq; Sun, 03 Feb 2019 15:57:08 +0000 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76] helo=wens.csie.org) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gqK8N-0000xA-5l for linux-arm-kernel@lists.infradead.org; Sun, 03 Feb 2019 15:56:42 +0000 Received: by wens.csie.org (Postfix, from userid 1000) id 970E05F92C; Sun, 3 Feb 2019 23:56:28 +0800 (CST) From: Chen-Yu Tsai To: Ulf Hansson , Maxime Ripard Subject: [PATCH 1/3] mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default Date: Sun, 3 Feb 2019 23:56:26 +0800 Message-Id: <20190203155628.16767-2-wens@csie.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203155628.16767-1-wens@csie.org> References: <20190203155628.16767-1-wens@csie.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190203_075639_382440_A1C05C81 X-CRM114-Status: GOOD ( 11.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Chris Blake , linux-mmc@vger.kernel.org, linux-sunxi@googlegroups.com, stable@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Some H5 boards seem to not have proper trace lengths for eMMC to be able to use the default setting for the delay chains under HS-DDR mode. These include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre Computer ALL-H3-CC-H5 works just fine. For the H5 (at least for now), default to not enabling HS-DDR modes in the driver, and expect the device tree to signal HS-DDR capability on boards that work. Reported-by: Chris Blake Fixes: 07bafc1e3536 ("mmc: sunxi: Use new timing mode for A64 eMMC controller") Cc: Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- drivers/mmc/host/sunxi-mmc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 279e326e397e..7415af8c8ff6 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -1399,7 +1399,16 @@ static int sunxi_mmc_probe(struct platform_device *pdev) mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; - if (host->cfg->clk_delays || host->use_new_timings) + /* + * Some H5 devices do not have signal traces precise enough to + * use HS DDR mode for their eMMC chips. + * + * We still enable HS DDR modes for all the other controller + * variants that support them. + */ + if ((host->cfg->clk_delays || host->use_new_timings) && + !of_device_is_compatible(pdev->dev.of_node, + "allwinner,sun50i-h5-emmc")) mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; ret = mmc_of_parse(mmc);