| Message ID | 1549272007-33471-4-git-send-email-biju.das@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add CMT/TMU support for RZ/G2E | expand |
Hi Biju, On Mon, Feb 4, 2019 at 10:25 AM Biju Das <biju.das@bp.renesas.com> wrote: > This patch adds TMU clock to the R8A774C0 SoC. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > --- > V1-->V2 Incorporated Geert's review comment. Thanks for the update! Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in clk-renesas-for-v5.1. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 4f3111b..aeadb4d 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -122,6 +122,11 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { + DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C), + DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C), + DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C), + DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2C), + DEF_MOD("tmu0", 125, R8A774C0_CLK_CP), DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C), DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C), DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
This patch adds TMU clock to the R8A774C0 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> --- V1-->V2 Incorporated Geert's review comment. --- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 5 +++++ 1 file changed, 5 insertions(+)