| Message ID | 20190207173230.22368-11-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/13] drm/i915: Don't pass crtc to intel_find_shared_dpll() | expand |
On Thu, Feb 7, 2019 at 9:33 AM Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The readout code thinks that kdiv of 3 is 4. Fix it. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_ddi.c | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 638a586469f9..f8c15148927a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9741,7 +9741,7 @@ enum skl_power_gate { > #define DPLL_CFGCR1_KDIV(x) ((x) << 6) > #define DPLL_CFGCR1_KDIV_1 (1 << 6) > #define DPLL_CFGCR1_KDIV_2 (2 << 6) > -#define DPLL_CFGCR1_KDIV_4 (4 << 6) > +#define DPLL_CFGCR1_KDIV_3 (4 << 6) > #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) > #define DPLL_CFGCR1_PDIV_SHIFT (2) > #define DPLL_CFGCR1_PDIV(x) ((x) << 2) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index ca705546a0ab..fd192baf93b2 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1349,8 +1349,8 @@ int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, > case DPLL_CFGCR1_KDIV_2: > p2 = 2; > break; > - case DPLL_CFGCR1_KDIV_4: > - p2 = 4; > + case DPLL_CFGCR1_KDIV_3: > + p2 = 3; confusing in the spec because kdiv 3 has the value 4. And no idea why we call it p2 rather than kdiv, that IMO whould make more sense. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi > break; > } > > -- > 2.19.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 638a586469f9..f8c15148927a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9741,7 +9741,7 @@ enum skl_power_gate { #define DPLL_CFGCR1_KDIV(x) ((x) << 6) #define DPLL_CFGCR1_KDIV_1 (1 << 6) #define DPLL_CFGCR1_KDIV_2 (2 << 6) -#define DPLL_CFGCR1_KDIV_4 (4 << 6) +#define DPLL_CFGCR1_KDIV_3 (4 << 6) #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) #define DPLL_CFGCR1_PDIV_SHIFT (2) #define DPLL_CFGCR1_PDIV(x) ((x) << 2) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index ca705546a0ab..fd192baf93b2 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1349,8 +1349,8 @@ int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, case DPLL_CFGCR1_KDIV_2: p2 = 2; break; - case DPLL_CFGCR1_KDIV_4: - p2 = 4; + case DPLL_CFGCR1_KDIV_3: + p2 = 3; break; }