[3/4] drm/v3d: Don't change other values in V3D_CTL_MISCCFG.
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Message ID 20190207201001.5730-3-eric@anholt.net
State New
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Series
  • [1/4] drm/v3d: Update top-level kerneldoc for the addition of TFU.
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Commit Message

Eric Anholt Feb. 7, 2019, 8:10 p.m. UTC
The register now has another field, QRMAXCNT for how many TMU requests
get serviced before thread switch.  We were accidentally reducing it
from its default of 0x3 (4 requests) to 0x0 (1).

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/v3d/v3d_gem.c  | 4 +++-
 drivers/gpu/drm/v3d/v3d_regs.h | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
index 3ee3ae4d3cac..887b4cf7020d 100644
--- a/drivers/gpu/drm/v3d/v3d_gem.c
+++ b/drivers/gpu/drm/v3d/v3d_gem.c
@@ -25,7 +25,9 @@  v3d_init_core(struct v3d_dev *v3d, int core)
 	 * type.  If you want the default behavior, you can still put
 	 * "2" in the indirect texture state's output_type field.
 	 */
-	V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT);
+	V3D_CORE_WRITE(core, V3D_CTL_MISCCFG,
+		       V3D_CORE_READ(core, V3D_CTL_MISCCFG) |
+		       V3D_MISCCFG_OVRTMUOUT);
 
 	/* Whenever we flush the L2T cache, we always want to flush
 	 * the whole thing.
diff --git a/drivers/gpu/drm/v3d/v3d_regs.h b/drivers/gpu/drm/v3d/v3d_regs.h
index 6ccdee9d47bd..8e88af237610 100644
--- a/drivers/gpu/drm/v3d/v3d_regs.h
+++ b/drivers/gpu/drm/v3d/v3d_regs.h
@@ -216,6 +216,8 @@ 
 # define V3D_IDENT2_BCG_INT                            BIT(28)
 
 #define V3D_CTL_MISCCFG                                0x00018
+# define V3D_CTL_MISCCFG_QRMAXCNT_MASK                 V3D_MASK(3, 1)
+# define V3D_CTL_MISCCFG_QRMAXCNT_SHIFT                1
 # define V3D_MISCCFG_OVRTMUOUT                         BIT(0)
 
 #define V3D_CTL_L2CACTL                                0x00020