diff mbox series

[6/6] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs

Message ID 20190207222428.16785-6-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/6] drm/i915: Compute has_drrs after compute has_psr | expand

Commit Message

Souza, Jose Feb. 7, 2019, 10:24 p.m. UTC 
This interlaced restriction applies to all gens, not only to Haswell.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 086d498362b6..c80352069232 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -607,8 +607,7 @@  void intel_psr_compute_config(struct intel_dp *intel_dp,
 		return;
 	}
 
-	if (IS_HASWELL(dev_priv) &&
-	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 		return;
 	}