| Message ID | 20190208150935.32108-3-thierry.reding@gmail.com (mailing list archive) |
|---|---|
| State | Mainlined, archived |
| Commit | 43c36002b86d6027b48f7c68ac32245f73f29f6b |
| Headers | show |
| Series | Tegra changes for v5.1-rc1 | expand |
On Fri, Feb 8, 2019 at 4:09 PM Thierry Reding <thierry.reding@gmail.com> wrote: > > Hi ARM SoC maintainers, > > The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c: > > Linux 5.0-rc1 (2019-01-06 17:08:20 -0800) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.1-cpufreq > > for you to fetch changes up to 43c36002b86d6027b48f7c68ac32245f73f29f6b: > > cpufreq: dt-platdev: add Tegra210 to blacklist (2019-02-06 14:31:19 +0100) > > Thanks, > Thierry > > ---------------------------------------------------------------- > cpufreq: tegra: Add support for Tegra210 > > This uses the DFLL clock support to enable CPU frequency scaling on > Tegra210. I see the Ack from Viresh, but I don't see why you'd like to have them merged through the soc tree rather than the cpufreq tree. Could you clarify? It's no problem to do it, I just want to make sure there is a good reason for it. Arnd
On Fri, Feb 15, 2019 at 5:28 PM Arnd Bergmann <arnd@arndb.de> wrote: > > On Fri, Feb 8, 2019 at 4:09 PM Thierry Reding <thierry.reding@gmail.com> wrote: > > > > Hi ARM SoC maintainers, > > > > The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c: > > > > Linux 5.0-rc1 (2019-01-06 17:08:20 -0800) > > > > are available in the Git repository at: > > > > git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.1-cpufreq > > > > for you to fetch changes up to 43c36002b86d6027b48f7c68ac32245f73f29f6b: > > > > cpufreq: dt-platdev: add Tegra210 to blacklist (2019-02-06 14:31:19 +0100) > > > > Thanks, > > Thierry > > > > ---------------------------------------------------------------- > > cpufreq: tegra: Add support for Tegra210 > > > > This uses the DFLL clock support to enable CPU frequency scaling on > > Tegra210. > > I see the Ack from Viresh, but I don't see why you'd like to have them > merged through the soc tree rather than the cpufreq tree. > > Could you clarify? It's no problem to do it, I just want to make sure > there is a good reason for it. Nevermind, I just found the 0/9 message that explains it all, pulled now into arm/drivers. Arnd
Hi ARM SoC maintainers, The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c: Linux 5.0-rc1 (2019-01-06 17:08:20 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.1-cpufreq for you to fetch changes up to 43c36002b86d6027b48f7c68ac32245f73f29f6b: cpufreq: dt-platdev: add Tegra210 to blacklist (2019-02-06 14:31:19 +0100) Thanks, Thierry ---------------------------------------------------------------- cpufreq: tegra: Add support for Tegra210 This uses the DFLL clock support to enable CPU frequency scaling on Tegra210. ---------------------------------------------------------------- Joseph Lo (3): cpufreq: tegra124: do not handle the CPU rail cpufreq: tegra124: extend to support Tegra210 cpufreq: dt-platdev: add Tegra210 to blacklist drivers/cpufreq/Kconfig.arm | 4 ++-- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/tegra124-cpufreq.c | 44 ++++-------------------------------- 3 files changed, 7 insertions(+), 42 deletions(-)