| Message ID | 20190213165424.22904-3-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] Revert "drm/i915: W/A for underruns with WM1+ disabled on icl" | expand |
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> -Clint On 2/13/19 8:54 AM, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The new workaround from the hw team involves programming the > leaving WM1 still disabled but programming the blocks value > identically to WM0, and we also need to set the "ignore > lines watermark" bit for WM1. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 7dd2ab0ca21b..4c0e43caa5cd 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4466,6 +4466,13 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, > for_each_plane_id_on_crtc(intel_crtc, plane_id) { > wm = &cstate->wm.skl.optimal.planes[plane_id]; > memset(&wm->wm[level], 0, sizeof(wm->wm[level])); > + > + /* W/A for underruns with WM1+ disabled */ > + if (IS_ICELAKE(dev_priv) && > + level == 1 && wm->wm[0].plane_en) { > + wm->wm[level].plane_res_b = wm->wm[0].plane_res_b; > + wm->wm[level].ignore_lines = true; > + } > } > } >
Tested with dual CRTC configuration shows many FIFO underruns even with this code. Single CRTC has not produced a FIFO underrun yet. [ 7037.510737] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe A FIFO underrun [ 7040.769741] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe A FIFO underrun [ 7042.029447] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe B FIFO underrun [ 7056.579801] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe A FIFO underrun [ 7057.105212] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe B FIFO underrun [ 7063.600646] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe A FIFO underrun [ 7072.373733] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe B FIFO underrun -Clint On 2/13/19 12:04 PM, Clinton Taylor wrote: > Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> > > -Clint > > On 2/13/19 8:54 AM, Ville Syrjala wrote: >> From: Ville Syrjälä <ville.syrjala@linux.intel.com> >> >> The new workaround from the hw team involves programming the >> leaving WM1 still disabled but programming the blocks value >> identically to WM0, and we also need to set the "ignore >> lines watermark" bit for WM1. >> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >> --- >> drivers/gpu/drm/i915/intel_pm.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c >> b/drivers/gpu/drm/i915/intel_pm.c >> index 7dd2ab0ca21b..4c0e43caa5cd 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -4466,6 +4466,13 @@ skl_allocate_pipe_ddb(struct intel_crtc_state >> *cstate, >> for_each_plane_id_on_crtc(intel_crtc, plane_id) { >> wm = &cstate->wm.skl.optimal.planes[plane_id]; >> memset(&wm->wm[level], 0, sizeof(wm->wm[level])); >> + >> + /* W/A for underruns with WM1+ disabled */ >> + if (IS_ICELAKE(dev_priv) && >> + level == 1 && wm->wm[0].plane_en) { >> + wm->wm[level].plane_res_b = wm->wm[0].plane_res_b; >> + wm->wm[level].ignore_lines = true; >> + } >> } >> } > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7dd2ab0ca21b..4c0e43caa5cd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4466,6 +4466,13 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, for_each_plane_id_on_crtc(intel_crtc, plane_id) { wm = &cstate->wm.skl.optimal.planes[plane_id]; memset(&wm->wm[level], 0, sizeof(wm->wm[level])); + + /* W/A for underruns with WM1+ disabled */ + if (IS_ICELAKE(dev_priv) && + level == 1 && wm->wm[0].plane_en) { + wm->wm[level].plane_res_b = wm->wm[0].plane_res_b; + wm->wm[level].ignore_lines = true; + } } }