[4/4] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
diff mbox series

Message ID 20190214130910.9201-5-tiny.windzz@gmail.com
State New
Headers show
Series
  • arm64: dts: allwinner: h6: Enable CPU DVFS(cpufreq)
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Commit Message

Frank Lee Feb. 14, 2019, 1:09 p.m. UTC
Add an OPP (Operating Performance Points) table for the CPU cores to
enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This
information comes from github.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++
 1 file changed, 61 insertions(+)

Comments

Maxime Ripard Feb. 14, 2019, 2:38 p.m. UTC | #1
Hi,

On Thu, Feb 14, 2019 at 08:09:10AM -0500, Yangtao Li wrote:
> Add an OPP (Operating Performance Points) table for the CPU cores to
> enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This
> information comes from github.
> 
> Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++
>  1 file changed, 61 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 57a1390ecdc2..46a4a69eb38f 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -28,6 +28,8 @@
>  			enable-method = "psci";
>  			clocks = <&ccu CLK_CPUX>; 
>  			clock-latency-ns = <244144>; /* 8 32k periods */
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu1: cpu@1 {
> @@ -37,6 +39,8 @@
>  			enable-method = "psci";
>  			clocks = <&ccu CLK_CPUX>; 
>  			clock-latency-ns = <244144>; /* 8 32k periods */
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu2: cpu@2 {
> @@ -46,6 +50,8 @@
>  			enable-method = "psci";
>  			clocks = <&ccu CLK_CPUX>; 
>  			clock-latency-ns = <244144>; /* 8 32k periods */
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu3: cpu@3 {
> @@ -55,6 +61,61 @@
>  			enable-method = "psci";
>  			clocks = <&ccu CLK_CPUX>; 
>  			clock-latency-ns = <244144>; /* 8 32k periods */
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
> +		};
> +	};
> +
> +	cpu_opp_table: opp_table {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@480000000 {
> +			opp-hz = /bits/ 64 <480000000>;
> +			opp-microvolt = <800000 800000 880000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@720000000 {
> +			opp-hz = /bits/ 64 <720000000>;
> +			opp-microvolt = <800000 800000 880000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@816000000 {
> +			opp-hz = /bits/ 64 <816000000>;
> +			opp-microvolt = <800000 800000 880000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@888000000 {
> +			opp-hz = /bits/ 64 <888000000>;
> +			opp-microvolt = <800000 800000 940000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@1080000000 {
> +			opp-hz = /bits/ 64 <1080000000>;
> +			opp-microvolt = <840000 840000 1060000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@1320000000 {
> +			opp-hz = /bits/ 64 <1320000000>;
> +			opp-microvolt = <900000 900000 1160000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@1488000000 {
> +			opp-hz = /bits/ 64 <1488000000>;
> +			opp-microvolt = <960000 960000 1160000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@1800000000 {
> +			opp-hz = /bits/ 64 <1800000000>;
> +			opp-microvolt = <1060000 1060000 1160000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */

So we definitely want to have that tested, especially since cpufreq
can lead to all kind of hard to debug errors (brown-outs, CPU lockups,
cache corruption, etc.). I good way to test that would be to use
cpufreq-ljt-stress-test here:
https://github.com/ssvb/cpuburn-arm/blob/master/cpufreq-ljt-stress-test

I'm especially worried about the higher frequencies that will probably
make the SoC heat too much

Maxime
Frank Lee Feb. 14, 2019, 2:52 p.m. UTC | #2
On Thu, Feb 14, 2019 at 10:38 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> Hi,
>
> On Thu, Feb 14, 2019 at 08:09:10AM -0500, Yangtao Li wrote:
> > Add an OPP (Operating Performance Points) table for the CPU cores to
> > enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This
> > information comes from github.
> >
> > Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
> > ---
> >  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++
> >  1 file changed, 61 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index 57a1390ecdc2..46a4a69eb38f 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -28,6 +28,8 @@
> >                       enable-method = "psci";
> >                       clocks = <&ccu CLK_CPUX>;
> >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     operating-points-v2 = <&cpu_opp_table>;
> > +                     #cooling-cells = <2>;
> >               };
> >
> >               cpu1: cpu@1 {
> > @@ -37,6 +39,8 @@
> >                       enable-method = "psci";
> >                       clocks = <&ccu CLK_CPUX>;
> >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     operating-points-v2 = <&cpu_opp_table>;
> > +                     #cooling-cells = <2>;
> >               };
> >
> >               cpu2: cpu@2 {
> > @@ -46,6 +50,8 @@
> >                       enable-method = "psci";
> >                       clocks = <&ccu CLK_CPUX>;
> >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     operating-points-v2 = <&cpu_opp_table>;
> > +                     #cooling-cells = <2>;
> >               };
> >
> >               cpu3: cpu@3 {
> > @@ -55,6 +61,61 @@
> >                       enable-method = "psci";
> >                       clocks = <&ccu CLK_CPUX>;
> >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     operating-points-v2 = <&cpu_opp_table>;
> > +                     #cooling-cells = <2>;
> > +             };
> > +     };
> > +
> > +     cpu_opp_table: opp_table {
> > +             compatible = "operating-points-v2";
> > +             opp-shared;
> > +
> > +             opp@480000000 {
> > +                     opp-hz = /bits/ 64 <480000000>;
> > +                     opp-microvolt = <800000 800000 880000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@720000000 {
> > +                     opp-hz = /bits/ 64 <720000000>;
> > +                     opp-microvolt = <800000 800000 880000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@816000000 {
> > +                     opp-hz = /bits/ 64 <816000000>;
> > +                     opp-microvolt = <800000 800000 880000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@888000000 {
> > +                     opp-hz = /bits/ 64 <888000000>;
> > +                     opp-microvolt = <800000 800000 940000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@1080000000 {
> > +                     opp-hz = /bits/ 64 <1080000000>;
> > +                     opp-microvolt = <840000 840000 1060000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@1320000000 {
> > +                     opp-hz = /bits/ 64 <1320000000>;
> > +                     opp-microvolt = <900000 900000 1160000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@1488000000 {
> > +                     opp-hz = /bits/ 64 <1488000000>;
> > +                     opp-microvolt = <960000 960000 1160000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@1800000000 {
> > +                     opp-hz = /bits/ 64 <1800000000>;
> > +                     opp-microvolt = <1060000 1060000 1160000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
>
> So we definitely want to have that tested, especially since cpufreq
> can lead to all kind of hard to debug errors (brown-outs, CPU lockups,
> cache corruption, etc.). I good way to test that would be to use
> cpufreq-ljt-stress-test here:
> https://github.com/ssvb/cpuburn-arm/blob/master/cpufreq-ljt-stress-test
>
> I'm especially worried about the higher frequencies that will probably
> make the SoC heat too much
Indeed, in order to avoid this situation, it is best to have cpu cooling
support(But now it does not support thermal driver? ).


In this case, perhaps we should remove the frequency beyond a certain
range to avoid the CPU being too hot?

Yangtao
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
Frank Lee Feb. 14, 2019, 4:56 p.m. UTC | #3
HI Maxime,

How about to implement a thermal driver that is not integrated with gpadc ?

GPADC on soc is rarely used now.

MBR,
Yangtao
Maxime Ripard Feb. 15, 2019, 1:53 p.m. UTC | #4
On Thu, Feb 14, 2019 at 10:52:16PM +0800, Frank Lee wrote:
> On Thu, Feb 14, 2019 at 10:38 PM Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> >
> > Hi,
> >
> > On Thu, Feb 14, 2019 at 08:09:10AM -0500, Yangtao Li wrote:
> > > Add an OPP (Operating Performance Points) table for the CPU cores to
> > > enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This
> > > information comes from github.
> > >
> > > Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
> > > ---
> > >  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++
> > >  1 file changed, 61 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > index 57a1390ecdc2..46a4a69eb38f 100644
> > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > @@ -28,6 +28,8 @@
> > >                       enable-method = "psci";
> > >                       clocks = <&ccu CLK_CPUX>;
> > >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > > +                     operating-points-v2 = <&cpu_opp_table>;
> > > +                     #cooling-cells = <2>;
> > >               };
> > >
> > >               cpu1: cpu@1 {
> > > @@ -37,6 +39,8 @@
> > >                       enable-method = "psci";
> > >                       clocks = <&ccu CLK_CPUX>;
> > >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > > +                     operating-points-v2 = <&cpu_opp_table>;
> > > +                     #cooling-cells = <2>;
> > >               };
> > >
> > >               cpu2: cpu@2 {
> > > @@ -46,6 +50,8 @@
> > >                       enable-method = "psci";
> > >                       clocks = <&ccu CLK_CPUX>;
> > >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > > +                     operating-points-v2 = <&cpu_opp_table>;
> > > +                     #cooling-cells = <2>;
> > >               };
> > >
> > >               cpu3: cpu@3 {
> > > @@ -55,6 +61,61 @@
> > >                       enable-method = "psci";
> > >                       clocks = <&ccu CLK_CPUX>;
> > >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > > +                     operating-points-v2 = <&cpu_opp_table>;
> > > +                     #cooling-cells = <2>;
> > > +             };
> > > +     };
> > > +
> > > +     cpu_opp_table: opp_table {
> > > +             compatible = "operating-points-v2";
> > > +             opp-shared;
> > > +
> > > +             opp@480000000 {
> > > +                     opp-hz = /bits/ 64 <480000000>;
> > > +                     opp-microvolt = <800000 800000 880000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@720000000 {
> > > +                     opp-hz = /bits/ 64 <720000000>;
> > > +                     opp-microvolt = <800000 800000 880000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@816000000 {
> > > +                     opp-hz = /bits/ 64 <816000000>;
> > > +                     opp-microvolt = <800000 800000 880000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@888000000 {
> > > +                     opp-hz = /bits/ 64 <888000000>;
> > > +                     opp-microvolt = <800000 800000 940000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1080000000 {
> > > +                     opp-hz = /bits/ 64 <1080000000>;
> > > +                     opp-microvolt = <840000 840000 1060000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1320000000 {
> > > +                     opp-hz = /bits/ 64 <1320000000>;
> > > +                     opp-microvolt = <900000 900000 1160000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1488000000 {
> > > +                     opp-hz = /bits/ 64 <1488000000>;
> > > +                     opp-microvolt = <960000 960000 1160000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1800000000 {
> > > +                     opp-hz = /bits/ 64 <1800000000>;
> > > +                     opp-microvolt = <1060000 1060000 1160000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> >
> > So we definitely want to have that tested, especially since cpufreq
> > can lead to all kind of hard to debug errors (brown-outs, CPU lockups,
> > cache corruption, etc.). I good way to test that would be to use
> > cpufreq-ljt-stress-test here:
> > https://github.com/ssvb/cpuburn-arm/blob/master/cpufreq-ljt-stress-test
> >
> > I'm especially worried about the higher frequencies that will probably
> > make the SoC heat too much
>
> Indeed, in order to avoid this situation, it is best to have cpu cooling
> support(But now it does not support thermal driver? ).
> 
> In this case, perhaps we should remove the frequency beyond a certain
> range to avoid the CPU being too hot?

Yeah, that seems like a nice solution until we have the thermal sensor
running.

Maxime
Maxime Ripard Feb. 15, 2019, 1:56 p.m. UTC | #5
Hi

On Fri, Feb 15, 2019 at 12:56:03AM +0800, Frank Lee wrote:
> How about to implement a thermal driver that is not integrated with
> gpadc ?
> 
> GPADC on soc is rarely used now.

You mean GPADC in general, or the gpadc driver in particular?
Otherwise, yes, having a driver for the thermal sensor in the H6
sounds like a good plan for thermal throttling, but I don't see it as
a dependency for that whole series.

Maxime
Frank Lee Feb. 15, 2019, 2:09 p.m. UTC | #6
On Fri, Feb 15, 2019 at 9:56 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> Hi
>
> On Fri, Feb 15, 2019 at 12:56:03AM +0800, Frank Lee wrote:
> > How about to implement a thermal driver that is not integrated with
> > gpadc ?
> >
> > GPADC on soc is rarely used now.
>
> You mean GPADC in general, or the gpadc driver in particular?
> Otherwise, yes, having a driver for the thermal sensor in the H6
> sounds like a good plan for thermal throttling, but I don't see it as
> a dependency for that whole series.
At present, sunxi's thermal driver is integrated with the gpadc driver.
I have a idea to implement the thermal driver alone. I haven't started yet,
and it may take a while to do it.

How about the plan to implement a thermal drive alone and put i
under drivers/thermal?

In addition to the cpu dvfs of H6, patch v2 has been sent.

Thanks,
Yangtao
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
Maxime Ripard Feb. 18, 2019, 9:33 a.m. UTC | #7
Hi,

On Fri, Feb 15, 2019 at 10:09:51PM +0800, Frank Lee wrote:
> On Fri, Feb 15, 2019 at 9:56 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > Hi
> >
> > On Fri, Feb 15, 2019 at 12:56:03AM +0800, Frank Lee wrote:
> > > How about to implement a thermal driver that is not integrated with
> > > gpadc ?
> > >
> > > GPADC on soc is rarely used now.
> >
> > You mean GPADC in general, or the gpadc driver in particular?
> > Otherwise, yes, having a driver for the thermal sensor in the H6
> > sounds like a good plan for thermal throttling, but I don't see it as
> > a dependency for that whole series.
>
> At present, sunxi's thermal driver is integrated with the gpadc driver.
> I have a idea to implement the thermal driver alone. I haven't started yet,
> and it may take a while to do it.
> 
> How about the plan to implement a thermal drive alone and put i
> under drivers/thermal?

The Thermal Sensor is basically a stripped down GPADC, which is why it
would make sense to have a single driver.

There was a pending series doing this that could be a good idea to
improve and merge:
https://lkml.org/lkml/2018/8/30/729

Maxime

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 57a1390ecdc2..46a4a69eb38f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -28,6 +28,8 @@ 
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>; 
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu1: cpu@1 {
@@ -37,6 +39,8 @@ 
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>; 
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu2: cpu@2 {
@@ -46,6 +50,8 @@ 
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>; 
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu@3 {
@@ -55,6 +61,61 @@ 
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>; 
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	cpu_opp_table: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <800000 800000 880000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@720000000 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <800000 800000 880000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <800000 800000 880000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@888000000 {
+			opp-hz = /bits/ 64 <888000000>;
+			opp-microvolt = <800000 800000 940000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1080000000 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <840000 840000 1060000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1320000000 {
+			opp-hz = /bits/ 64 <1320000000>;
+			opp-microvolt = <900000 900000 1160000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1488000000 {
+			opp-hz = /bits/ 64 <1488000000>;
+			opp-microvolt = <960000 960000 1160000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1800000000 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1060000 1060000 1160000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 	};