| Message ID | 1550233589-13891-1-git-send-email-fabrizio.castro@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 12ce412b2cc6aea88c9c93e6303372f72014efc6 |
| Delegated to: | Simon Horman |
| Headers | show |
| Series | arm64: dts: renesas: r8a774c0: Fix cpu nodes style | expand |
On Fri, Feb 15, 2019 at 1:26 PM Fabrizio Castro <fabrizio.castro@bp.renesas.com> wrote: > We usually leave a space between "=" and the value of device > tree properties, but unfortunately that was overlooked for the > "clocks" property of cpu@0 and cpu@1. > This patch fixes the spacing with the "clocks" property of > cpu@0 and cpu@1. > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Hello Simon, Are you happy with this patch? Thanks, Fab > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > Sent: 15 February 2019 12:26 > Subject: [PATCH] arm64: dts: renesas: r8a774c0: Fix cpu nodes style > > We usually leave a space between "=" and the value of device > tree properties, but unfortunately that was overlooked for the > "clocks" property of cpu@0 and cpu@1. > This patch fixes the spacing with the "clocks" property of > cpu@0 and cpu@1. > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > --- > arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > index 61a0afb..0bbcaf1 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > @@ -76,7 +76,7 @@ > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; > + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; > operating-points-v2 = <&cluster1_opp>; > }; > > @@ -87,7 +87,7 @@ > power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; > + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; > operating-points-v2 = <&cluster1_opp>; > }; > > -- > 2.7.4
On Fri, Mar 01, 2019 at 12:00:39PM +0000, Fabrizio Castro wrote: > Hello Simon, > > Are you happy with this patch? > > Thanks, > Fab > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > Sent: 15 February 2019 12:26 > > Subject: [PATCH] arm64: dts: renesas: r8a774c0: Fix cpu nodes style > > > > We usually leave a space between "=" and the value of device > > tree properties, but unfortunately that was overlooked for the > > "clocks" property of cpu@0 and cpu@1. > > This patch fixes the spacing with the "clocks" property of > > cpu@0 and cpu@1. > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Thanks, and sorry for the delay. Applied for v5.2. > > --- > > arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > > index 61a0afb..0bbcaf1 100644 > > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > > @@ -76,7 +76,7 @@ > > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; > > next-level-cache = <&L2_CA53>; > > enable-method = "psci"; > > - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; > > + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; > > operating-points-v2 = <&cluster1_opp>; > > }; > > > > @@ -87,7 +87,7 @@ > > power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; > > next-level-cache = <&L2_CA53>; > > enable-method = "psci"; > > - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; > > + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; > > operating-points-v2 = <&cluster1_opp>; > > }; > > > > -- > > 2.7.4 >
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 61a0afb..0bbcaf1 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -76,7 +76,7 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -87,7 +87,7 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; };
We usually leave a space between "=" and the value of device tree properties, but unfortunately that was overlooked for the "clocks" property of cpu@0 and cpu@1. This patch fixes the spacing with the "clocks" property of cpu@0 and cpu@1. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)