| Message ID | 1550338640-17470-14-git-send-email-ramalingam.c@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Implement HDCP2.2 | expand |
On Sat, 16 Feb 2019, Ramalingam C via dri-devel <dri-devel@lists.freedesktop.org> wrote: > Implements the DP adaptation specific HDCP2.2 functions. > > These functions perform the DPCD read and write for communicating the > HDCP2.2 auth message back and forth. > > v2: > wait for cp_irq is merged with this patch. Rebased. > v3: > wait_queue is used for wait for cp_irq [Chris Wilson] > v4: > Style fixed. > %s/PARING/PAIRING > Few style fixes [Uma] > v5: > Lookup table for DP HDCP2.2 msg details [Daniel]. > Extra lines are removed. > v6: Rebased. > v7: > Fixed some regression introduced at v5. [Ankit] > Macro HDCP_2_2_RX_CAPS_VERSION_VAL is reused [Uma] > Converted a function to inline [Uma] > %s/uintxx_t/uxx > v8: > Error due to the sinks are reported as DEBUG logs. > Adjust to the new mei interface. > v9: > ARRAY_SIZE for no of array members [Jon & Daniel] > return of the wait_for_cp_irq is made as void [Daniel] > Wait for HDCP2.2 msg is done based on polling the reg bit than > CP_IRQ based. [Daniel] > hdcp adaptation is added as a const in the hdcp_shim [Daniel] > v10: > config_stream_type is redefined [Daniel] > DP Errata specific defines are moved into intel_dp.c. > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > Signed-off-by: Ankit K Nautiyal <ankit.k.nautiyal@intel.com> > Reviewed-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 333 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 333 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 9f73a4239574..e9fe25f21200 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -5847,6 +5847,333 @@ int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, > return 0; > } > > +struct hdcp2_dp_errata_stream_type { > + u8 msg_id; > + u8 stream_type; > +} __packed; > + > +static struct hdcp2_dp_msg_data { > + u8 msg_id; > + u32 offset; > + bool msg_detectable; > + u32 timeout; > + u32 timeout2; /* Added for non_paired situation */ > + } hdcp2_msg_data[] = { > + {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0}, > + {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, > + false, HDCP_2_2_CERT_TIMEOUT_MS, 0}, > + {HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, > + false, 0, 0}, > + {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, > + false, 0, 0}, > + {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, > + true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, > + HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS}, > + {HDCP_2_2_AKE_SEND_PAIRING_INFO, > + DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, > + HDCP_2_2_PAIRING_TIMEOUT_MS, 0}, > + {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0}, > + {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, > + false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0}, > + {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, > + 0, 0}, > + {HDCP_2_2_REP_SEND_RECVID_LIST, > + DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, > + HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0}, > + {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, > + 0, 0}, > + {HDCP_2_2_REP_STREAM_MANAGE, > + DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, > + 0, 0}, > + {HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, > + false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0}, > +/* local define to shovel this through the write_2_2 interface */ > +#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 > + {HDCP_2_2_ERRATA_DP_STREAM_TYPE, > + DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, > + 0, 0}, > + }; Hate to bring this up so far after this has been merged, but hdcp2_msg_data[] must be moved out of driver static data. BR, Jani. > + > +static inline > +int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, > + u8 *rx_status) > +{ > + ssize_t ret; > + > + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > + DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, > + HDCP_2_2_DP_RXSTATUS_LEN); > + if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { > + DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); > + return ret >= 0 ? -EIO : ret; > + } > + > + return 0; > +} > + > +static > +int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, > + u8 msg_id, bool *msg_ready) > +{ > + u8 rx_status; > + int ret; > + > + *msg_ready = false; > + ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); > + if (ret < 0) > + return ret; > + > + switch (msg_id) { > + case HDCP_2_2_AKE_SEND_HPRIME: > + if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) > + *msg_ready = true; > + break; > + case HDCP_2_2_AKE_SEND_PAIRING_INFO: > + if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) > + *msg_ready = true; > + break; > + case HDCP_2_2_REP_SEND_RECVID_LIST: > + if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) > + *msg_ready = true; > + break; > + default: > + DRM_ERROR("Unidentified msg_id: %d\n", msg_id); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static ssize_t > +intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, > + struct hdcp2_dp_msg_data *hdcp2_msg_data) > +{ > + struct intel_dp *dp = &intel_dig_port->dp; > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; > + u8 msg_id = hdcp2_msg_data->msg_id; > + int ret, timeout; > + bool msg_ready = false; > + > + if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) > + timeout = hdcp2_msg_data->timeout2; > + else > + timeout = hdcp2_msg_data->timeout; > + > + /* > + * There is no way to detect the CERT, LPRIME and STREAM_READY > + * availability. So Wait for timeout and read the msg. > + */ > + if (!hdcp2_msg_data->msg_detectable) { > + mdelay(timeout); > + ret = 0; > + } else { > + /* TODO: In case if you need to wait on CP_IRQ, do it here */ > + ret = __wait_for(ret = > + hdcp2_detect_msg_availability(intel_dig_port, > + msg_id, > + &msg_ready), > + !ret && msg_ready, timeout * 1000, > + 1000, 5 * 1000); > + > + if (!msg_ready) > + ret = -ETIMEDOUT; > + } > + > + if (ret) > + DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n", > + hdcp2_msg_data->msg_id, ret, timeout); > + > + return ret; > +} > + > +static struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++) > + if (hdcp2_msg_data[i].msg_id == msg_id) > + return &hdcp2_msg_data[i]; > + > + return NULL; > +} > + > +static > +int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, > + void *buf, size_t size) > +{ > + unsigned int offset; > + u8 *byte = buf; > + ssize_t ret, bytes_to_write, len; > + struct hdcp2_dp_msg_data *hdcp2_msg_data; > + > + hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); > + if (!hdcp2_msg_data) > + return -EINVAL; > + > + offset = hdcp2_msg_data->offset; > + > + /* No msg_id in DP HDCP2.2 msgs */ > + bytes_to_write = size - 1; > + byte++; > + > + while (bytes_to_write) { > + len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? > + DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; > + > + ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, > + offset, (void *)byte, len); > + if (ret < 0) > + return ret; > + > + bytes_to_write -= ret; > + byte += ret; > + offset += ret; > + } > + > + return size; > +} > + > +static > +ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) > +{ > + u8 rx_info[HDCP_2_2_RXINFO_LEN]; > + u32 dev_cnt; > + ssize_t ret; > + > + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > + DP_HDCP_2_2_REG_RXINFO_OFFSET, > + (void *)rx_info, HDCP_2_2_RXINFO_LEN); > + if (ret != HDCP_2_2_RXINFO_LEN) > + return ret >= 0 ? -EIO : ret; > + > + dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | > + HDCP_2_2_DEV_COUNT_LO(rx_info[1])); > + > + if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) > + dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; > + > + ret = sizeof(struct hdcp2_rep_send_receiverid_list) - > + HDCP_2_2_RECEIVER_IDS_MAX_LEN + > + (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); > + > + return ret; > +} > + > +static > +int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, > + u8 msg_id, void *buf, size_t size) > +{ > + unsigned int offset; > + u8 *byte = buf; > + ssize_t ret, bytes_to_recv, len; > + struct hdcp2_dp_msg_data *hdcp2_msg_data; > + > + hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); > + if (!hdcp2_msg_data) > + return -EINVAL; > + offset = hdcp2_msg_data->offset; > + > + ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); > + if (ret < 0) > + return ret; > + > + if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { > + ret = get_receiver_id_list_size(intel_dig_port); > + if (ret < 0) > + return ret; > + > + size = ret; > + } > + bytes_to_recv = size - 1; > + > + /* DP adaptation msgs has no msg_id */ > + byte++; > + > + while (bytes_to_recv) { > + len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? > + DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; > + > + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, > + (void *)byte, len); > + if (ret < 0) { > + DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret); > + return ret; > + } > + > + bytes_to_recv -= ret; > + byte += ret; > + offset += ret; > + } > + byte = buf; > + *byte = msg_id; > + > + return size; > +} > + > +static > +int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, > + bool is_repeater, u8 content_type) > +{ > + struct hdcp2_dp_errata_stream_type stream_type_msg; > + > + if (is_repeater) > + return 0; > + > + /* > + * Errata for DP: As Stream type is used for encryption, Receiver > + * should be communicated with stream type for the decryption of the > + * content. > + * Repeater will be communicated with stream type as a part of it's > + * auth later in time. > + */ > + stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; > + stream_type_msg.stream_type = content_type; > + > + return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, > + sizeof(stream_type_msg)); > +} > + > +static > +int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) > +{ > + u8 rx_status; > + int ret; > + > + ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); > + if (ret) > + return ret; > + > + if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) > + ret = HDCP_REAUTH_REQUEST; > + else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) > + ret = HDCP_LINK_INTEGRITY_FAILURE; > + else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) > + ret = HDCP_TOPOLOGY_CHANGE; > + > + return ret; > +} > + > +static > +int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, > + bool *capable) > +{ > + u8 rx_caps[3]; > + int ret; > + > + *capable = false; > + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > + DP_HDCP_2_2_REG_RX_CAPS_OFFSET, > + rx_caps, HDCP_2_2_RXCAPS_LEN); > + if (ret != HDCP_2_2_RXCAPS_LEN) > + return ret >= 0 ? -EIO : ret; > + > + if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && > + HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) > + *capable = true; > + > + return 0; > +} > + > static const struct intel_hdcp_shim intel_dp_hdcp_shim = { > .write_an_aksv = intel_dp_hdcp_write_an_aksv, > .read_bksv = intel_dp_hdcp_read_bksv, > @@ -5859,6 +6186,12 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = { > .toggle_signalling = intel_dp_hdcp_toggle_signalling, > .check_link = intel_dp_hdcp_check_link, > .hdcp_capable = intel_dp_hdcp_capable, > + .write_2_2_msg = intel_dp_hdcp2_write_msg, > + .read_2_2_msg = intel_dp_hdcp2_read_msg, > + .config_stream_type = intel_dp_hdcp2_config_stream_type, > + .check_2_2_link = intel_dp_hdcp2_check_link, > + .hdcp_2_2_capable = intel_dp_hdcp2_capable, > + .protocol = HDCP_PROTOCOL_DP, > }; > > static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
On 2019-08-15 at 11:43:54 +0300, Jani Nikula wrote: > On Sat, 16 Feb 2019, Ramalingam C via dri-devel <dri-devel@lists.freedesktop.org> wrote: > > Implements the DP adaptation specific HDCP2.2 functions. > > > > These functions perform the DPCD read and write for communicating the > > HDCP2.2 auth message back and forth. > > > > v2: > > wait for cp_irq is merged with this patch. Rebased. > > v3: > > wait_queue is used for wait for cp_irq [Chris Wilson] > > v4: > > Style fixed. > > %s/PARING/PAIRING > > Few style fixes [Uma] > > v5: > > Lookup table for DP HDCP2.2 msg details [Daniel]. > > Extra lines are removed. > > v6: Rebased. > > v7: > > Fixed some regression introduced at v5. [Ankit] > > Macro HDCP_2_2_RX_CAPS_VERSION_VAL is reused [Uma] > > Converted a function to inline [Uma] > > %s/uintxx_t/uxx > > v8: > > Error due to the sinks are reported as DEBUG logs. > > Adjust to the new mei interface. > > v9: > > ARRAY_SIZE for no of array members [Jon & Daniel] > > return of the wait_for_cp_irq is made as void [Daniel] > > Wait for HDCP2.2 msg is done based on polling the reg bit than > > CP_IRQ based. [Daniel] > > hdcp adaptation is added as a const in the hdcp_shim [Daniel] > > v10: > > config_stream_type is redefined [Daniel] > > DP Errata specific defines are moved into intel_dp.c. > > > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > > Signed-off-by: Ankit K Nautiyal <ankit.k.nautiyal@intel.com> > > Reviewed-by: Uma Shankar <uma.shankar@intel.com> > > --- > > drivers/gpu/drm/i915/intel_dp.c | 333 ++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 333 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index 9f73a4239574..e9fe25f21200 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -5847,6 +5847,333 @@ int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, > > return 0; > > } > > > > +struct hdcp2_dp_errata_stream_type { > > + u8 msg_id; > > + u8 stream_type; > > +} __packed; > > + > > +static struct hdcp2_dp_msg_data { > > + u8 msg_id; > > + u32 offset; > > + bool msg_detectable; > > + u32 timeout; > > + u32 timeout2; /* Added for non_paired situation */ > > + } hdcp2_msg_data[] = { > > + {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0}, > > + {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, > > + false, HDCP_2_2_CERT_TIMEOUT_MS, 0}, > > + {HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, > > + false, 0, 0}, > > + {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, > > + false, 0, 0}, > > + {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, > > + true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, > > + HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS}, > > + {HDCP_2_2_AKE_SEND_PAIRING_INFO, > > + DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, > > + HDCP_2_2_PAIRING_TIMEOUT_MS, 0}, > > + {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0}, > > + {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, > > + false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0}, > > + {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, > > + 0, 0}, > > + {HDCP_2_2_REP_SEND_RECVID_LIST, > > + DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, > > + HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0}, > > + {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, > > + 0, 0}, > > + {HDCP_2_2_REP_STREAM_MANAGE, > > + DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, > > + 0, 0}, > > + {HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, > > + false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0}, > > +/* local define to shovel this through the write_2_2 interface */ > > +#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 > > + {HDCP_2_2_ERRATA_DP_STREAM_TYPE, > > + DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, > > + 0, 0}, > > + }; > > Hate to bring this up so far after this has been merged, but > hdcp2_msg_data[] must be moved out of driver static data. Jani, Could you please explain why we dont like it? Alternate i could think immediately is populate the messages in the runtime based on the msg_id using the functions and use them. -Ram > > BR, > Jani. > > > > + > > +static inline > > +int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, > > + u8 *rx_status) > > +{ > > + ssize_t ret; > > + > > + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > > + DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, > > + HDCP_2_2_DP_RXSTATUS_LEN); > > + if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { > > + DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); > > + return ret >= 0 ? -EIO : ret; > > + } > > + > > + return 0; > > +} > > + > > +static > > +int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, > > + u8 msg_id, bool *msg_ready) > > +{ > > + u8 rx_status; > > + int ret; > > + > > + *msg_ready = false; > > + ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); > > + if (ret < 0) > > + return ret; > > + > > + switch (msg_id) { > > + case HDCP_2_2_AKE_SEND_HPRIME: > > + if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) > > + *msg_ready = true; > > + break; > > + case HDCP_2_2_AKE_SEND_PAIRING_INFO: > > + if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) > > + *msg_ready = true; > > + break; > > + case HDCP_2_2_REP_SEND_RECVID_LIST: > > + if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) > > + *msg_ready = true; > > + break; > > + default: > > + DRM_ERROR("Unidentified msg_id: %d\n", msg_id); > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static ssize_t > > +intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, > > + struct hdcp2_dp_msg_data *hdcp2_msg_data) > > +{ > > + struct intel_dp *dp = &intel_dig_port->dp; > > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; > > + u8 msg_id = hdcp2_msg_data->msg_id; > > + int ret, timeout; > > + bool msg_ready = false; > > + > > + if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) > > + timeout = hdcp2_msg_data->timeout2; > > + else > > + timeout = hdcp2_msg_data->timeout; > > + > > + /* > > + * There is no way to detect the CERT, LPRIME and STREAM_READY > > + * availability. So Wait for timeout and read the msg. > > + */ > > + if (!hdcp2_msg_data->msg_detectable) { > > + mdelay(timeout); > > + ret = 0; > > + } else { > > + /* TODO: In case if you need to wait on CP_IRQ, do it here */ > > + ret = __wait_for(ret = > > + hdcp2_detect_msg_availability(intel_dig_port, > > + msg_id, > > + &msg_ready), > > + !ret && msg_ready, timeout * 1000, > > + 1000, 5 * 1000); > > + > > + if (!msg_ready) > > + ret = -ETIMEDOUT; > > + } > > + > > + if (ret) > > + DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n", > > + hdcp2_msg_data->msg_id, ret, timeout); > > + > > + return ret; > > +} > > + > > +static struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) > > +{ > > + int i; > > + > > + for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++) > > + if (hdcp2_msg_data[i].msg_id == msg_id) > > + return &hdcp2_msg_data[i]; > > + > > + return NULL; > > +} > > + > > +static > > +int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, > > + void *buf, size_t size) > > +{ > > + unsigned int offset; > > + u8 *byte = buf; > > + ssize_t ret, bytes_to_write, len; > > + struct hdcp2_dp_msg_data *hdcp2_msg_data; > > + > > + hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); > > + if (!hdcp2_msg_data) > > + return -EINVAL; > > + > > + offset = hdcp2_msg_data->offset; > > + > > + /* No msg_id in DP HDCP2.2 msgs */ > > + bytes_to_write = size - 1; > > + byte++; > > + > > + while (bytes_to_write) { > > + len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? > > + DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; > > + > > + ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, > > + offset, (void *)byte, len); > > + if (ret < 0) > > + return ret; > > + > > + bytes_to_write -= ret; > > + byte += ret; > > + offset += ret; > > + } > > + > > + return size; > > +} > > + > > +static > > +ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) > > +{ > > + u8 rx_info[HDCP_2_2_RXINFO_LEN]; > > + u32 dev_cnt; > > + ssize_t ret; > > + > > + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > > + DP_HDCP_2_2_REG_RXINFO_OFFSET, > > + (void *)rx_info, HDCP_2_2_RXINFO_LEN); > > + if (ret != HDCP_2_2_RXINFO_LEN) > > + return ret >= 0 ? -EIO : ret; > > + > > + dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | > > + HDCP_2_2_DEV_COUNT_LO(rx_info[1])); > > + > > + if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) > > + dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; > > + > > + ret = sizeof(struct hdcp2_rep_send_receiverid_list) - > > + HDCP_2_2_RECEIVER_IDS_MAX_LEN + > > + (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); > > + > > + return ret; > > +} > > + > > +static > > +int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, > > + u8 msg_id, void *buf, size_t size) > > +{ > > + unsigned int offset; > > + u8 *byte = buf; > > + ssize_t ret, bytes_to_recv, len; > > + struct hdcp2_dp_msg_data *hdcp2_msg_data; > > + > > + hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); > > + if (!hdcp2_msg_data) > > + return -EINVAL; > > + offset = hdcp2_msg_data->offset; > > + > > + ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); > > + if (ret < 0) > > + return ret; > > + > > + if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { > > + ret = get_receiver_id_list_size(intel_dig_port); > > + if (ret < 0) > > + return ret; > > + > > + size = ret; > > + } > > + bytes_to_recv = size - 1; > > + > > + /* DP adaptation msgs has no msg_id */ > > + byte++; > > + > > + while (bytes_to_recv) { > > + len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? > > + DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; > > + > > + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, > > + (void *)byte, len); > > + if (ret < 0) { > > + DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret); > > + return ret; > > + } > > + > > + bytes_to_recv -= ret; > > + byte += ret; > > + offset += ret; > > + } > > + byte = buf; > > + *byte = msg_id; > > + > > + return size; > > +} > > + > > +static > > +int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, > > + bool is_repeater, u8 content_type) > > +{ > > + struct hdcp2_dp_errata_stream_type stream_type_msg; > > + > > + if (is_repeater) > > + return 0; > > + > > + /* > > + * Errata for DP: As Stream type is used for encryption, Receiver > > + * should be communicated with stream type for the decryption of the > > + * content. > > + * Repeater will be communicated with stream type as a part of it's > > + * auth later in time. > > + */ > > + stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; > > + stream_type_msg.stream_type = content_type; > > + > > + return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, > > + sizeof(stream_type_msg)); > > +} > > + > > +static > > +int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) > > +{ > > + u8 rx_status; > > + int ret; > > + > > + ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); > > + if (ret) > > + return ret; > > + > > + if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) > > + ret = HDCP_REAUTH_REQUEST; > > + else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) > > + ret = HDCP_LINK_INTEGRITY_FAILURE; > > + else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) > > + ret = HDCP_TOPOLOGY_CHANGE; > > + > > + return ret; > > +} > > + > > +static > > +int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, > > + bool *capable) > > +{ > > + u8 rx_caps[3]; > > + int ret; > > + > > + *capable = false; > > + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > > + DP_HDCP_2_2_REG_RX_CAPS_OFFSET, > > + rx_caps, HDCP_2_2_RXCAPS_LEN); > > + if (ret != HDCP_2_2_RXCAPS_LEN) > > + return ret >= 0 ? -EIO : ret; > > + > > + if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && > > + HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) > > + *capable = true; > > + > > + return 0; > > +} > > + > > static const struct intel_hdcp_shim intel_dp_hdcp_shim = { > > .write_an_aksv = intel_dp_hdcp_write_an_aksv, > > .read_bksv = intel_dp_hdcp_read_bksv, > > @@ -5859,6 +6186,12 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = { > > .toggle_signalling = intel_dp_hdcp_toggle_signalling, > > .check_link = intel_dp_hdcp_check_link, > > .hdcp_capable = intel_dp_hdcp_capable, > > + .write_2_2_msg = intel_dp_hdcp2_write_msg, > > + .read_2_2_msg = intel_dp_hdcp2_read_msg, > > + .config_stream_type = intel_dp_hdcp2_config_stream_type, > > + .check_2_2_link = intel_dp_hdcp2_check_link, > > + .hdcp_2_2_capable = intel_dp_hdcp2_capable, > > + .protocol = HDCP_PROTOCOL_DP, > > }; > > > > static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) > > -- > Jani Nikula, Intel Open Source Graphics Center
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 9f73a4239574..e9fe25f21200 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5847,6 +5847,333 @@ int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, return 0; } +struct hdcp2_dp_errata_stream_type { + u8 msg_id; + u8 stream_type; +} __packed; + +static struct hdcp2_dp_msg_data { + u8 msg_id; + u32 offset; + bool msg_detectable; + u32 timeout; + u32 timeout2; /* Added for non_paired situation */ + } hdcp2_msg_data[] = { + {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0}, + {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, + false, HDCP_2_2_CERT_TIMEOUT_MS, 0}, + {HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, + false, 0, 0}, + {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, + false, 0, 0}, + {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, + true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, + HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS}, + {HDCP_2_2_AKE_SEND_PAIRING_INFO, + DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, + HDCP_2_2_PAIRING_TIMEOUT_MS, 0}, + {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0}, + {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, + false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0}, + {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, + 0, 0}, + {HDCP_2_2_REP_SEND_RECVID_LIST, + DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, + HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0}, + {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, + 0, 0}, + {HDCP_2_2_REP_STREAM_MANAGE, + DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, + 0, 0}, + {HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, + false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0}, +/* local define to shovel this through the write_2_2 interface */ +#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 + {HDCP_2_2_ERRATA_DP_STREAM_TYPE, + DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, + 0, 0}, + }; + +static inline +int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, + u8 *rx_status) +{ + ssize_t ret; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, + HDCP_2_2_DP_RXSTATUS_LEN); + if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { + DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); + return ret >= 0 ? -EIO : ret; + } + + return 0; +} + +static +int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, + u8 msg_id, bool *msg_ready) +{ + u8 rx_status; + int ret; + + *msg_ready = false; + ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); + if (ret < 0) + return ret; + + switch (msg_id) { + case HDCP_2_2_AKE_SEND_HPRIME: + if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) + *msg_ready = true; + break; + case HDCP_2_2_AKE_SEND_PAIRING_INFO: + if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) + *msg_ready = true; + break; + case HDCP_2_2_REP_SEND_RECVID_LIST: + if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) + *msg_ready = true; + break; + default: + DRM_ERROR("Unidentified msg_id: %d\n", msg_id); + return -EINVAL; + } + + return 0; +} + +static ssize_t +intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, + struct hdcp2_dp_msg_data *hdcp2_msg_data) +{ + struct intel_dp *dp = &intel_dig_port->dp; + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; + u8 msg_id = hdcp2_msg_data->msg_id; + int ret, timeout; + bool msg_ready = false; + + if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) + timeout = hdcp2_msg_data->timeout2; + else + timeout = hdcp2_msg_data->timeout; + + /* + * There is no way to detect the CERT, LPRIME and STREAM_READY + * availability. So Wait for timeout and read the msg. + */ + if (!hdcp2_msg_data->msg_detectable) { + mdelay(timeout); + ret = 0; + } else { + /* TODO: In case if you need to wait on CP_IRQ, do it here */ + ret = __wait_for(ret = + hdcp2_detect_msg_availability(intel_dig_port, + msg_id, + &msg_ready), + !ret && msg_ready, timeout * 1000, + 1000, 5 * 1000); + + if (!msg_ready) + ret = -ETIMEDOUT; + } + + if (ret) + DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n", + hdcp2_msg_data->msg_id, ret, timeout); + + return ret; +} + +static struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++) + if (hdcp2_msg_data[i].msg_id == msg_id) + return &hdcp2_msg_data[i]; + + return NULL; +} + +static +int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, + void *buf, size_t size) +{ + unsigned int offset; + u8 *byte = buf; + ssize_t ret, bytes_to_write, len; + struct hdcp2_dp_msg_data *hdcp2_msg_data; + + hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); + if (!hdcp2_msg_data) + return -EINVAL; + + offset = hdcp2_msg_data->offset; + + /* No msg_id in DP HDCP2.2 msgs */ + bytes_to_write = size - 1; + byte++; + + while (bytes_to_write) { + len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? + DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; + + ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, + offset, (void *)byte, len); + if (ret < 0) + return ret; + + bytes_to_write -= ret; + byte += ret; + offset += ret; + } + + return size; +} + +static +ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) +{ + u8 rx_info[HDCP_2_2_RXINFO_LEN]; + u32 dev_cnt; + ssize_t ret; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + DP_HDCP_2_2_REG_RXINFO_OFFSET, + (void *)rx_info, HDCP_2_2_RXINFO_LEN); + if (ret != HDCP_2_2_RXINFO_LEN) + return ret >= 0 ? -EIO : ret; + + dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | + HDCP_2_2_DEV_COUNT_LO(rx_info[1])); + + if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) + dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; + + ret = sizeof(struct hdcp2_rep_send_receiverid_list) - + HDCP_2_2_RECEIVER_IDS_MAX_LEN + + (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); + + return ret; +} + +static +int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, + u8 msg_id, void *buf, size_t size) +{ + unsigned int offset; + u8 *byte = buf; + ssize_t ret, bytes_to_recv, len; + struct hdcp2_dp_msg_data *hdcp2_msg_data; + + hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); + if (!hdcp2_msg_data) + return -EINVAL; + offset = hdcp2_msg_data->offset; + + ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); + if (ret < 0) + return ret; + + if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { + ret = get_receiver_id_list_size(intel_dig_port); + if (ret < 0) + return ret; + + size = ret; + } + bytes_to_recv = size - 1; + + /* DP adaptation msgs has no msg_id */ + byte++; + + while (bytes_to_recv) { + len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? + DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, + (void *)byte, len); + if (ret < 0) { + DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret); + return ret; + } + + bytes_to_recv -= ret; + byte += ret; + offset += ret; + } + byte = buf; + *byte = msg_id; + + return size; +} + +static +int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, + bool is_repeater, u8 content_type) +{ + struct hdcp2_dp_errata_stream_type stream_type_msg; + + if (is_repeater) + return 0; + + /* + * Errata for DP: As Stream type is used for encryption, Receiver + * should be communicated with stream type for the decryption of the + * content. + * Repeater will be communicated with stream type as a part of it's + * auth later in time. + */ + stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; + stream_type_msg.stream_type = content_type; + + return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, + sizeof(stream_type_msg)); +} + +static +int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) +{ + u8 rx_status; + int ret; + + ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); + if (ret) + return ret; + + if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) + ret = HDCP_REAUTH_REQUEST; + else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) + ret = HDCP_LINK_INTEGRITY_FAILURE; + else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) + ret = HDCP_TOPOLOGY_CHANGE; + + return ret; +} + +static +int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, + bool *capable) +{ + u8 rx_caps[3]; + int ret; + + *capable = false; + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + DP_HDCP_2_2_REG_RX_CAPS_OFFSET, + rx_caps, HDCP_2_2_RXCAPS_LEN); + if (ret != HDCP_2_2_RXCAPS_LEN) + return ret >= 0 ? -EIO : ret; + + if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && + HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) + *capable = true; + + return 0; +} + static const struct intel_hdcp_shim intel_dp_hdcp_shim = { .write_an_aksv = intel_dp_hdcp_write_an_aksv, .read_bksv = intel_dp_hdcp_read_bksv, @@ -5859,6 +6186,12 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = { .toggle_signalling = intel_dp_hdcp_toggle_signalling, .check_link = intel_dp_hdcp_check_link, .hdcp_capable = intel_dp_hdcp_capable, + .write_2_2_msg = intel_dp_hdcp2_write_msg, + .read_2_2_msg = intel_dp_hdcp2_read_msg, + .config_stream_type = intel_dp_hdcp2_config_stream_type, + .check_2_2_link = intel_dp_hdcp2_check_link, + .hdcp_2_2_capable = intel_dp_hdcp2_capable, + .protocol = HDCP_PROTOCOL_DP, }; static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
Implements the DP adaptation specific HDCP2.2 functions. These functions perform the DPCD read and write for communicating the HDCP2.2 auth message back and forth. v2: wait for cp_irq is merged with this patch. Rebased. v3: wait_queue is used for wait for cp_irq [Chris Wilson] v4: Style fixed. %s/PARING/PAIRING Few style fixes [Uma] v5: Lookup table for DP HDCP2.2 msg details [Daniel]. Extra lines are removed. v6: Rebased. v7: Fixed some regression introduced at v5. [Ankit] Macro HDCP_2_2_RX_CAPS_VERSION_VAL is reused [Uma] Converted a function to inline [Uma] %s/uintxx_t/uxx v8: Error due to the sinks are reported as DEBUG logs. Adjust to the new mei interface. v9: ARRAY_SIZE for no of array members [Jon & Daniel] return of the wait_for_cp_irq is made as void [Daniel] Wait for HDCP2.2 msg is done based on polling the reg bit than CP_IRQ based. [Daniel] hdcp adaptation is added as a const in the hdcp_shim [Daniel] v10: config_stream_type is redefined [Daniel] DP Errata specific defines are moved into intel_dp.c. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Ankit K Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 333 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 333 insertions(+)