| Message ID | 1550570914-26391-4-git-send-email-claudiu.beznea@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add support for the new SAM9X60's PWM controller | expand |
On Tue, Feb 19, 2019 at 10:09:00AM +0000, Claudiu.Beznea@microchip.com wrote: > From: Claudiu Beznea <claudiu.beznea@microchip.com> > > Add support for SAM9X60's PWM controller. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > drivers/pwm/pwm-atmel.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c > index 647d063562db..229cedb02770 100644 > --- a/drivers/pwm/pwm-atmel.c > +++ b/drivers/pwm/pwm-atmel.c > @@ -52,6 +52,8 @@ > > /* Only the LSB 16 bits are significant. */ > #define PWM_MAXV1_PRD 0xFFFF > +/* All 32 bits are significant. */ > +#define PWM_MAXV2_PRD 0xFFFFFFFF > #define PRD_MAXV1_PRES 10 > > struct atmel_pwm_registers { > @@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { > }, > }; > > +static const struct atmel_pwm_data atmel_pwm_data_v3 = { Does it make more sense to call this ..._sam9x60 to match the compatible? (If yes, patch 1 should be changed accordingly.) I wonder how the naming of the defines is chosen given that pwm_data_v3 is the first that needs PWM_MAXV2_PRD. Looks inconsistent. Best regards Uwe
On 21.02.2019 22:45, Uwe Kleine-König wrote: > On Tue, Feb 19, 2019 at 10:09:00AM +0000, Claudiu.Beznea@microchip.com wrote: >> From: Claudiu Beznea <claudiu.beznea@microchip.com> >> >> Add support for SAM9X60's PWM controller. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> >> --- >> drivers/pwm/pwm-atmel.c | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c >> index 647d063562db..229cedb02770 100644 >> --- a/drivers/pwm/pwm-atmel.c >> +++ b/drivers/pwm/pwm-atmel.c >> @@ -52,6 +52,8 @@ >> >> /* Only the LSB 16 bits are significant. */ >> #define PWM_MAXV1_PRD 0xFFFF >> +/* All 32 bits are significant. */ >> +#define PWM_MAXV2_PRD 0xFFFFFFFF >> #define PRD_MAXV1_PRES 10 >> >> struct atmel_pwm_registers { >> @@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { >> }, >> }; >> >> +static const struct atmel_pwm_data atmel_pwm_data_v3 = { > > Does it make more sense to call this ..._sam9x60 to match the > compatible? (If yes, patch 1 should be changed accordingly.) It could be changed, yep. > > I wonder how the naming of the defines is chosen given that pwm_data_v3 > is the first that needs PWM_MAXV2_PRD. Looks inconsistent. I know... I'm aware of that. The thing is controllers may differ with regards to in-flight duty update and now there is this new difference w/ regards to counters size. Renaming the objects of type atmel_pwm_data in something like atmel_pwm_data_<chip-name> as you suggested before would make things clear for you? Thank you, Claudiu Beznea > > Best regards > Uwe >
Hello, On Fri, Feb 22, 2019 at 09:07:57AM +0000, Claudiu.Beznea@microchip.com wrote: > On 21.02.2019 22:45, Uwe Kleine-König wrote: > > On Tue, Feb 19, 2019 at 10:09:00AM +0000, Claudiu.Beznea@microchip.com wrote: > > I wonder how the naming of the defines is chosen given that pwm_data_v3 > > is the first that needs PWM_MAXV2_PRD. Looks inconsistent. > > I know... I'm aware of that. The thing is controllers may differ with > regards to in-flight duty update and now there is this new difference w/ > regards to counters size. > > Renaming the objects of type atmel_pwm_data in something like > atmel_pwm_data_<chip-name> as you suggested before would make things clear > for you? Yes. Naming stuff after the first SoC that hat the respective feature/quirk/property should be fine. Best regards Uwe
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 647d063562db..229cedb02770 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -52,6 +52,8 @@ /* Only the LSB 16 bits are significant. */ #define PWM_MAXV1_PRD 0xFFFF +/* All 32 bits are significant. */ +#define PWM_MAXV2_PRD 0xFFFFFFFF #define PRD_MAXV1_PRES 10 struct atmel_pwm_registers { @@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { }, }; +static const struct atmel_pwm_data atmel_pwm_data_v3 = { + .regs = { + .period = PWMV1_CPRD, + .period_upd = PWMV1_CUPD, + .duty = PWMV1_CDTY, + .duty_upd = PWMV1_CUPD, + }, + .cfg = { + /* 32 bits to keep period and duty. */ + .max_period = PWM_MAXV2_PRD, + .max_pres = PRD_MAXV1_PRES, + }, +}; + static const struct platform_device_id atmel_pwm_devtypes[] = { { .name = "at91sam9rl-pwm", @@ -335,6 +351,9 @@ static const struct of_device_id atmel_pwm_dt_ids[] = { .compatible = "atmel,sama5d2-pwm", .data = &atmel_pwm_data_v2, }, { + .compatible = "microchip,sam9x60-pwm", + .data = &atmel_pwm_data_v3, + }, { /* sentinel */ }, };