@@ -4,12 +4,148 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
+#include <dt-bindings/firmware/imx/rsrc.h>
+
adma_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x2000000>;
+ /* SCU clocks */
+ adma_ipg_clk: clock-adma-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "adma_ipg_clk";
+ };
+
+ adc0_clk: clock-adc0 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_ADC_0>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "adc0_clk";
+ };
+
+ can0_clk: clock-can0 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_CAN_0>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "can0_clk";
+ };
+
+ ftm0_clk: clock-ftm0 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_FTM_0>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "ftm0_clk";
+ };
+
+ ftm1_clk: clock-ftm1 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_FTM_1>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "ftm1_clk";
+ };
+
+ i2c0_clk: clock-i2c0 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_I2C_0>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "i2c0_clk";
+ };
+
+ i2c1_clk: clock-i2c1 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_I2C_1>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "i2c1_clk";
+ };
+
+ i2c2_clk: clock-i2c2 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_I2C_2>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "i2c2_clk";
+ };
+
+ i2c3_clk: clock-i2c3 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_I2C_3>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "i2c3_clk";
+ };
+
+ lcd0_clk: clock-lcd0 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_LCD_0>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "lcd0_clk";
+ };
+
+ lcd0_pwm0_clk: clock-lcd0-pwm0 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_LCD_0_PWM_0>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "lcd0_pwm0_clk";
+ };
+
+ spi0_clk: clock-spi0 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_SPI_0>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "spi0_clk";
+ };
+
+ spi1_clk: clock-spi1 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_SPI_1>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "spi1_clk";
+ };
+
+ spi2_clk: clock-spi2 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_SPI_2>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "spi2_clk";
+ };
+
+ spi3_clk: clock-spi3 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_SPI_3>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "spi3_clk";
+ };
+
+ uart0_clk: clock-uart0 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_UART_0>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "uart0_clk";
+ };
+
+ uart1_clk: clock-uart1 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_UART_1>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "uart1_clk";
+ };
+
+ uart2_clk: clock-uart2 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_UART_2>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "uart2_clk";
+ };
+
+ uart3_clk: clock-uart3 {
+ #clock-cells = <0>;
+ rsrc-id = <IMX_SC_R_UART_3>;
+ clk-type = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "uart3_clk";
+ };
+
adma_lpcg: clock-controller@59000000 {
reg = <0x59000000 0x2000000>;
#clock-cells = <1>;
Add adma scu clocks Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 136 ++++++++++++++++++++++++ 1 file changed, 136 insertions(+)