[V7,1/2] arm64: dts: freescale: imx8qxp: add cpu opp table
diff mbox series

Message ID 1551157967-30925-1-git-send-email-Anson.Huang@nxp.com
State New
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Series
  • [V7,1/2] arm64: dts: freescale: imx8qxp: add cpu opp table
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Commit Message

Anson Huang Feb. 26, 2019, 5:17 a.m. UTC
Add i.MX8QXP CPU opp table to support cpufreq.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
No changes since V6.
---
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

Comments

Shawn Guo Feb. 28, 2019, 3:18 a.m. UTC | #1
On Tue, Feb 26, 2019 at 05:17:31AM +0000, Anson Huang wrote:
> Add i.MX8QXP CPU opp table to support cpufreq.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

Prefix 'arm64: dts: imx8qxp: ' would already be clear enough.  I dropped
'freescale' from there and applied patch.

> ---
> No changes since V6.
> ---
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 4c3dd95..41bf0ce 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -34,6 +34,9 @@
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
>  			next-level-cache = <&A35_L2>;
> +			clocks = <&clk IMX_A35_CLK>;
> +			operating-points-v2 = <&a35_0_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A35_1: cpu@1 {
> @@ -42,6 +45,9 @@
>  			reg = <0x0 0x1>;
>  			enable-method = "psci";
>  			next-level-cache = <&A35_L2>;
> +			clocks = <&clk IMX_A35_CLK>;
> +			operating-points-v2 = <&a35_0_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A35_2: cpu@2 {
> @@ -50,6 +56,9 @@
>  			reg = <0x0 0x2>;
>  			enable-method = "psci";
>  			next-level-cache = <&A35_L2>;
> +			clocks = <&clk IMX_A35_CLK>;
> +			operating-points-v2 = <&a35_0_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A35_3: cpu@3 {
> @@ -58,6 +67,9 @@
>  			reg = <0x0 0x3>;
>  			enable-method = "psci";
>  			next-level-cache = <&A35_L2>;
> +			clocks = <&clk IMX_A35_CLK>;
> +			operating-points-v2 = <&a35_0_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		A35_L2: l2-cache0 {
> @@ -65,6 +77,24 @@
>  		};
>  	};
>  
> +	a35_0_opp_table: opp-table {

What does the '0' in the label mean?

Shawn

> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-900000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			opp-microvolt = <1000000>;
> +			clock-latency-ns = <150000>;
> +		};
> +
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <150000>;
> +			opp-suspend;
> +		};
> +	};
> +
>  	gic: interrupt-controller@51a00000 {
>  		compatible = "arm,gic-v3";
>  		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> -- 
> 2.7.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Anson Huang Feb. 28, 2019, 6:18 a.m. UTC | #2
Hi, Shawn

Best Regards!
Anson Huang

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: 2019年2月28日 11:19
> To: Anson Huang <anson.huang@nxp.com>
> Cc: robh+dt@kernel.org; mark.rutland@arm.com; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; mturquette@baylibre.com;
> sboyd@kernel.org; Aisheng Dong <aisheng.dong@nxp.com>; Daniel Baluta
> <daniel.baluta@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> clk@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp
> table
> 
> On Tue, Feb 26, 2019 at 05:17:31AM +0000, Anson Huang wrote:
> > Add i.MX8QXP CPU opp table to support cpufreq.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> 
> Prefix 'arm64: dts: imx8qxp: ' would already be clear enough.  I dropped
> 'freescale' from there and applied patch.
> 
> > ---
> > No changes since V6.
> > ---
> >  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30
> > ++++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > index 4c3dd95..41bf0ce 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > @@ -34,6 +34,9 @@
> >  			reg = <0x0 0x0>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A35_L2>;
> > +			clocks = <&clk IMX_A35_CLK>;
> > +			operating-points-v2 = <&a35_0_opp_table>;
> > +			#cooling-cells = <2>;
> >  		};
> >
> >  		A35_1: cpu@1 {
> > @@ -42,6 +45,9 @@
> >  			reg = <0x0 0x1>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A35_L2>;
> > +			clocks = <&clk IMX_A35_CLK>;
> > +			operating-points-v2 = <&a35_0_opp_table>;
> > +			#cooling-cells = <2>;
> >  		};
> >
> >  		A35_2: cpu@2 {
> > @@ -50,6 +56,9 @@
> >  			reg = <0x0 0x2>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A35_L2>;
> > +			clocks = <&clk IMX_A35_CLK>;
> > +			operating-points-v2 = <&a35_0_opp_table>;
> > +			#cooling-cells = <2>;
> >  		};
> >
> >  		A35_3: cpu@3 {
> > @@ -58,6 +67,9 @@
> >  			reg = <0x0 0x3>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A35_L2>;
> > +			clocks = <&clk IMX_A35_CLK>;
> > +			operating-points-v2 = <&a35_0_opp_table>;
> > +			#cooling-cells = <2>;
> >  		};
> >
> >  		A35_L2: l2-cache0 {
> > @@ -65,6 +77,24 @@
> >  		};
> >  	};
> >
> > +	a35_0_opp_table: opp-table {
> 
> What does the '0' in the label mean?

Looks like the '0' in the label is NOT necessary, we can just use 'a35_opp_table',
do you want me resend the patch to remove '0'?

Anson.

> 
> Shawn
> 
> > +		compatible = "operating-points-v2";
> > +		opp-shared;
> > +
> > +		opp-900000000 {
> > +			opp-hz = /bits/ 64 <900000000>;
> > +			opp-microvolt = <1000000>;
> > +			clock-latency-ns = <150000>;
> > +		};
> > +
> > +		opp-1200000000 {
> > +			opp-hz = /bits/ 64 <1200000000>;
> > +			opp-microvolt = <1100000>;
> > +			clock-latency-ns = <150000>;
> > +			opp-suspend;
> > +		};
> > +	};
> > +
> >  	gic: interrupt-controller@51a00000 {
> >  		compatible = "arm,gic-v3";
> >  		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> > --
> > 2.7.4
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist
> > s.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-
> kernel&amp;data=02%7C
> >
> 01%7Canson.huang%40nxp.com%7Cfe4ff92a639e4739c2a108d69d2b8e12%7
> C686ea1
> >
> d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636869207728398808&amp;sd
> ata=oz%2
> > FPyAki6fkfQZqaSYkjWfo3m8S48sCzpDf2lxDIjKs%3D&amp;reserved=0
Shawn Guo Feb. 28, 2019, 6:42 a.m. UTC | #3
On Thu, Feb 28, 2019 at 06:18:30AM +0000, Anson Huang wrote:
> Hi, Shawn
> 
> Best Regards!
> Anson Huang
> 
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo@kernel.org]
> > Sent: 2019年2月28日 11:19
> > To: Anson Huang <anson.huang@nxp.com>
> > Cc: robh+dt@kernel.org; mark.rutland@arm.com; s.hauer@pengutronix.de;
> > kernel@pengutronix.de; festevam@gmail.com; mturquette@baylibre.com;
> > sboyd@kernel.org; Aisheng Dong <aisheng.dong@nxp.com>; Daniel Baluta
> > <daniel.baluta@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> > clk@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>
> > Subject: Re: [PATCH V7 1/2] arm64: dts: freescale: imx8qxp: add cpu opp
> > table
> > 
> > On Tue, Feb 26, 2019 at 05:17:31AM +0000, Anson Huang wrote:
> > > Add i.MX8QXP CPU opp table to support cpufreq.
> > >
> > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> > 
> > Prefix 'arm64: dts: imx8qxp: ' would already be clear enough.  I dropped
> > 'freescale' from there and applied patch.
> > 
> > > ---
> > > No changes since V6.
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30
> > > ++++++++++++++++++++++++++++++
> > >  1 file changed, 30 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > index 4c3dd95..41bf0ce 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > @@ -34,6 +34,9 @@
> > >  			reg = <0x0 0x0>;
> > >  			enable-method = "psci";
> > >  			next-level-cache = <&A35_L2>;
> > > +			clocks = <&clk IMX_A35_CLK>;
> > > +			operating-points-v2 = <&a35_0_opp_table>;
> > > +			#cooling-cells = <2>;
> > >  		};
> > >
> > >  		A35_1: cpu@1 {
> > > @@ -42,6 +45,9 @@
> > >  			reg = <0x0 0x1>;
> > >  			enable-method = "psci";
> > >  			next-level-cache = <&A35_L2>;
> > > +			clocks = <&clk IMX_A35_CLK>;
> > > +			operating-points-v2 = <&a35_0_opp_table>;
> > > +			#cooling-cells = <2>;
> > >  		};
> > >
> > >  		A35_2: cpu@2 {
> > > @@ -50,6 +56,9 @@
> > >  			reg = <0x0 0x2>;
> > >  			enable-method = "psci";
> > >  			next-level-cache = <&A35_L2>;
> > > +			clocks = <&clk IMX_A35_CLK>;
> > > +			operating-points-v2 = <&a35_0_opp_table>;
> > > +			#cooling-cells = <2>;
> > >  		};
> > >
> > >  		A35_3: cpu@3 {
> > > @@ -58,6 +67,9 @@
> > >  			reg = <0x0 0x3>;
> > >  			enable-method = "psci";
> > >  			next-level-cache = <&A35_L2>;
> > > +			clocks = <&clk IMX_A35_CLK>;
> > > +			operating-points-v2 = <&a35_0_opp_table>;
> > > +			#cooling-cells = <2>;
> > >  		};
> > >
> > >  		A35_L2: l2-cache0 {
> > > @@ -65,6 +77,24 @@
> > >  		};
> > >  	};
> > >
> > > +	a35_0_opp_table: opp-table {
> > 
> > What does the '0' in the label mean?
> 
> Looks like the '0' in the label is NOT necessary, we can just use 'a35_opp_table',
> do you want me resend the patch to remove '0'?

No.  I just fixed it up and applied the patch.

Shawn

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4c3dd95..41bf0ce 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -34,6 +34,9 @@ 
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			next-level-cache = <&A35_L2>;
+			clocks = <&clk IMX_A35_CLK>;
+			operating-points-v2 = <&a35_0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		A35_1: cpu@1 {
@@ -42,6 +45,9 @@ 
 			reg = <0x0 0x1>;
 			enable-method = "psci";
 			next-level-cache = <&A35_L2>;
+			clocks = <&clk IMX_A35_CLK>;
+			operating-points-v2 = <&a35_0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		A35_2: cpu@2 {
@@ -50,6 +56,9 @@ 
 			reg = <0x0 0x2>;
 			enable-method = "psci";
 			next-level-cache = <&A35_L2>;
+			clocks = <&clk IMX_A35_CLK>;
+			operating-points-v2 = <&a35_0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		A35_3: cpu@3 {
@@ -58,6 +67,9 @@ 
 			reg = <0x0 0x3>;
 			enable-method = "psci";
 			next-level-cache = <&A35_L2>;
+			clocks = <&clk IMX_A35_CLK>;
+			operating-points-v2 = <&a35_0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		A35_L2: l2-cache0 {
@@ -65,6 +77,24 @@ 
 		};
 	};
 
+	a35_0_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+	};
+
 	gic: interrupt-controller@51a00000 {
 		compatible = "arm,gic-v3";
 		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */