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Tue, 26 Feb 2019 07:08:14 +0000 From: Daniel Baluta To: "shawnguo@kernel.org" Subject: [PATCH v3 3/5] arm64: dts: imx8mq: Add SAI pinctrl configuration Thread-Topic: [PATCH v3 3/5] arm64: dts: imx8mq: Add SAI pinctrl configuration Thread-Index: AQHUzaIKxBjJrciaq0Gs2Sxh8vcUYw== Date: Tue, 26 Feb 2019 07:08:14 +0000 Message-ID: <20190226070742.30551-4-daniel.baluta@nxp.com> References: <20190226070742.30551-1-daniel.baluta@nxp.com> In-Reply-To: <20190226070742.30551-1-daniel.baluta@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR04CA0102.eurprd04.prod.outlook.com (2603:10a6:803:64::37) To VI1PR0402MB3357.eurprd04.prod.outlook.com (2603:10a6:803:2::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=daniel.baluta@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [95.76.156.53] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 14b6ef4e-1838-42d6-2062-08d69bb92ccc x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Wang" , "angus@akkea.ca" , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , Aisheng Dong , "agx@sigxcpu.org" , "festevam@gmail.com" , "s.hauer@pengutronix.de" , "linux-arm-kernel@lists.infradead.org" , "l.stach@pengutronix.de" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This sets the pin configuration for SAI pins BLCK/MCLK/FSYNC/DATA. GPIO_01 is used for mute. Signed-off-by: Daniel Baluta --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 54737bf1772f..d21ee2a5312c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -223,6 +223,16 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f