| Message ID | 20190226120633.18200-5-brgl@bgdev.pl (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: davinci: modernize the timer support | expand |
On 2/26/19 6:06 AM, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bgolaszewski@baylibre.com> > > We now have a proper clocksource driver for davinci. Switch the da850 > platform to using it. > > Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> > --- Reviewed-by: David Lechner <david@lechnology.com> > arch/arm/mach-davinci/da850.c | 41 ++++++++++------------------------- > 1 file changed, 11 insertions(+), 30 deletions(-) > > diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c > index 72d64d39d42a..5ce58ae0d764 100644 > --- a/arch/arm/mach-davinci/da850.c > +++ b/arch/arm/mach-davinci/da850.c > @@ -34,7 +34,8 @@ > #include <mach/cputype.h> > #include <mach/da8xx.h> > #include <mach/pm.h> > -#include <mach/time.h> > + > +#include <clocksource/timer-davinci.h> > > #include "irqs.h" > #include "mux.h" > @@ -332,38 +333,17 @@ static struct davinci_id da850_ids[] = { > }, > }; > > -static struct davinci_timer_instance da850_timer_instance[4] = { > - { > - .base = DA8XX_TIMER64P0_BASE, > - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0), > - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0), > - }, > - { > - .base = DA8XX_TIMER64P1_BASE, > - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1), > - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1), > - }, > - { > - .base = DA850_TIMER64P2_BASE, > - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2), > - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2), > - }, > - { > - .base = DA850_TIMER64P3_BASE, > - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3), > - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3), > - }, > -}; > - > /* > * T0_BOT: Timer 0, bottom : Used for clock_event > * T0_TOP: Timer 0, top : Used for clocksource > * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer It looks like we could drop the mention of the watchdog timer here. And T0_BOT/T0_TOP don't really have a meaning anymore. > */ > -static struct davinci_timer_info da850_timer_info = { > - .timers = da850_timer_instance, > - .clockevent_id = T0_BOT, > - .clocksource_id = T0_TOP, > +static const struct davinci_timer_cfg da850_timer_cfg = { > + .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), > + .irq = { > + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), > + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)), > + }, > };
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 72d64d39d42a..5ce58ae0d764 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -34,7 +34,8 @@ #include <mach/cputype.h> #include <mach/da8xx.h> #include <mach/pm.h> -#include <mach/time.h> + +#include <clocksource/timer-davinci.h> #include "irqs.h" #include "mux.h" @@ -332,38 +333,17 @@ static struct davinci_id da850_ids[] = { }, }; -static struct davinci_timer_instance da850_timer_instance[4] = { - { - .base = DA8XX_TIMER64P0_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0), - }, - { - .base = DA8XX_TIMER64P1_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1), - }, - { - .base = DA850_TIMER64P2_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2), - }, - { - .base = DA850_TIMER64P3_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3), - .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3), - }, -}; - /* * T0_BOT: Timer 0, bottom : Used for clock_event * T0_TOP: Timer 0, top : Used for clocksource * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer */ -static struct davinci_timer_info da850_timer_info = { - .timers = da850_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, +static const struct davinci_timer_cfg da850_timer_cfg = { + .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), + .irq = { + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), + DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)), + }, }; #ifdef CONFIG_CPU_FREQ @@ -634,7 +614,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da850_pins, .pinmux_pins_num = ARRAY_SIZE(da850_pins), - .timer_info = &da850_timer_info, .emac_pdata = &da8xx_emac_pdata, .sram_dma = DA8XX_SHARED_RAM_BASE, .sram_len = SZ_128K, @@ -671,6 +650,7 @@ void __init da850_init_time(void) void __iomem *pll0; struct regmap *cfgchip; struct clk *clk; + int rv; clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); @@ -685,7 +665,8 @@ void __init da850_init_time(void) return; } - davinci_timer_init(clk); + rv = davinci_timer_register(clk, &da850_timer_cfg); + WARN(rv, "Unable to register the timer: %d\n", rv); } static struct resource da850_pll1_resources[] = {