From patchwork Tue Feb 26 23:36:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kees Cook X-Patchwork-Id: 10830931 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A264C180E for ; Tue, 26 Feb 2019 23:37:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8F1522D734 for ; Tue, 26 Feb 2019 23:37:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 833652D738; Tue, 26 Feb 2019 23:37:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id C2EC02D739 for ; Tue, 26 Feb 2019 23:37:20 +0000 (UTC) Received: (qmail 32224 invoked by uid 550); 26 Feb 2019 23:37:09 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 32161 invoked from network); 26 Feb 2019 23:37:08 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+oYY7xbWtmy3I3xAdK40RKuX5lYtH9k01cC1Ag26GTE=; b=UFpQQXyv1WlG+vQ2VGQVeBpekJEgGJm2XiXC/0iqN9nei8flgJHMUhw+1gO/u6r5Z7 0vm0yI+z26dsUE9TactgLhLPQvgHVxBI9LzDiQ3XZ2VyxREYHaViUVTcnjLuZEl7BgO0 yrwaIBLzjSsVT03OTDfX79+D30OJwPVl2oPoA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+oYY7xbWtmy3I3xAdK40RKuX5lYtH9k01cC1Ag26GTE=; b=tsbqccE+WBt76eLtYf7l5QE+gpyK+OnMoziBYo4AvuhxIZh810FMhK9b+DINvoQCfQ vhXJnsr6BV7WOxNiUa9YwPQrJzq+5j2udhHAlVrlgGQAqOzVLHur1bfgV5O5M5xeCBVQ 9yymCIOUiRrFfGc3gvGjefYpxMD4e6p6YE2mnHL3rOp9szibcusFGHZJyT4wLAO7o1DT db5WbKUAMKP1swvoU2BRgHlapW92xdmfIhRfhgNUoyqS37H813QQOnIu6XOHHvBFhNeU 7VB9PqNFrnPhnN1d3E4xQXIZnCbeRloUVFvxDuawBCw9OijWQKZG7FHlBN5D9HV5hxaD VdMw== X-Gm-Message-State: AHQUAubdskuBminSEAlrQpSJKV2iJC8/ItvSFYKP2Abu0aDtPwooKcT4 ydZpWl4FEs0+ScqfTTaudaOI//WK4KA= X-Google-Smtp-Source: AHgI3IYxRjSOI0v0d+U8i/glfBS5fF/2id9Tw7ZYe31sT6gSxDF2rJYY5yfnK8VNxonTJyUxWqvduQ== X-Received: by 2002:a17:902:6b8c:: with SMTP id p12mr29293448plk.282.1551224217159; Tue, 26 Feb 2019 15:36:57 -0800 (PST) From: Kees Cook To: Thomas Gleixner Cc: Kees Cook , Peter Zijlstra , Jann Horn , Sean Christopherson , Dominik Brodowski , Kernel Hardening , linux-kernel@vger.kernel.org Subject: [PATCH 2/3] x86/asm: Avoid taking an exception before cr4 restore Date: Tue, 26 Feb 2019 15:36:46 -0800 Message-Id: <20190226233647.28547-3-keescook@chromium.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190226233647.28547-1-keescook@chromium.org> References: <20190226233647.28547-1-keescook@chromium.org> X-Virus-Scanned: ClamAV using ClamSMTP Instead of taking a full WARN() exception before restoring a potentially missed CR4 bit, this retains the missing bit for later reporting. This matches the logic done for the CR0 pinning. Signed-off-by: Kees Cook --- arch/x86/include/asm/special_insns.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 8416d6b31084..6f649eaecc73 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -97,6 +97,8 @@ extern volatile unsigned long cr4_pin; static inline void native_write_cr4(unsigned long val) { + unsigned long warn = 0; + again: val |= cr4_pin; asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order)); @@ -105,10 +107,12 @@ static inline void native_write_cr4(unsigned long val) * notice the lack of pinned bits in "val" and start the function * from the beginning to gain the cr4_pin bits for sure. */ - if (WARN_ONCE((val & cr4_pin) != cr4_pin, - "Attempt to unpin cr4 bits: %lx, cr4 bypass attack?!", - ~val & cr4_pin)) + if ((val & cr4_pin) != cr4_pin) { + warn = ~val & cr4_pin; goto again; + } + WARN_ONCE(warn, "Attempt to unpin cr4 bits: %lx; bypass attack?!\n", + warn); } #ifdef CONFIG_X86_64