diff mbox series

[v2,1/6] mmc: sdhci-of-esdhc: add erratum eSDHC5 support

Message ID 20190228073618.16061-1-yinbo.zhu@nxp.com (mailing list archive)
State New, archived
Headers show
Series [v2,1/6] mmc: sdhci-of-esdhc: add erratum eSDHC5 support | expand

Commit Message

Yinbo Zhu Feb. 28, 2019, 7:35 a.m. UTC 
From: Yinbo Zhu <yinbo.zhu@nxp.com>

Software writing to the Transfer Type configuration register
(system clock domain) can cause a setup/hold violation in the
CRC flops (card clock domain), which can cause write accesses
to be sent with corrupt CRC values. This issue occurs only for
write preceded by read. this erratum is to fix this issue.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
 drivers/mmc/host/sdhci-of-esdhc.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)
diff mbox series

Patch

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index 4e669b4..9da53e5 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -1074,6 +1074,9 @@  static int sdhci_esdhc_probe(struct platform_device *pdev)
 	if (esdhc->vendor_ver > VENDOR_V_22)
 		host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
 
+	if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc"))
+		host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
+
 	if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
 	    of_device_is_compatible(np, "fsl,p5020-esdhc") ||
 	    of_device_is_compatible(np, "fsl,p4080-esdhc") ||