From patchwork Sun Aug 21 16:02:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 1083512 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p7LFpELX016259 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Sun, 21 Aug 2011 15:51:35 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QvAIj-0006g4-LJ; Sun, 21 Aug 2011 15:51:05 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QvAIj-0003g2-6Y; Sun, 21 Aug 2011 15:51:05 +0000 Received: from va3ehsobe003.messaging.microsoft.com ([216.32.180.13] helo=VA3EHSOBE003.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QvAIe-0003fk-Iy for linux-arm-kernel@lists.infradead.org; Sun, 21 Aug 2011 15:51:02 +0000 Received: from mail150-va3-R.bigfish.com (10.7.14.239) by VA3EHSOBE003.bigfish.com (10.7.40.23) with Microsoft SMTP Server id 14.1.225.22; Sun, 21 Aug 2011 15:50:59 +0000 Received: from mail150-va3 (localhost.localdomain [127.0.0.1]) by mail150-va3-R.bigfish.com (Postfix) with ESMTP id 9B6ED9F84A9; Sun, 21 Aug 2011 15:50:58 +0000 (UTC) X-SpamScore: 6 X-BigFish: VS6(zzc8kzz1202h1082kzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail150-va3 (localhost.localdomain [127.0.0.1]) by mail150-va3 (MessageSwitch) id 1313941803652384_15933; Sun, 21 Aug 2011 15:50:03 +0000 (UTC) Received: from VA3EHSMHS009.bigfish.com (unknown [10.7.14.245]) by mail150-va3.bigfish.com (Postfix) with ESMTP id CD9F4132804F; Sun, 21 Aug 2011 15:50:02 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS009.bigfish.com (10.7.99.19) with Microsoft SMTP Server (TLS) id 14.1.225.22; Sun, 21 Aug 2011 15:50:02 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.2; Sun, 21 Aug 2011 10:50:01 -0500 Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p7LFnv3M013076; Sun, 21 Aug 2011 10:49:58 -0500 (CDT) From: Dong Aisheng To: Subject: [PATCH 1/2] ASoC: mxs-saif: add record function Date: Mon, 22 Aug 2011 00:02:25 +0800 Message-ID: <1313942545-21403-1-git-send-email-b29396@freescale.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110821_115100_790745_4B2D9EA4 X-CRM114-Status: GOOD ( 32.00 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.180.13 listed in list.dnswl.org] Cc: s.hauer@pengutronix.de, broonie@opensource.wolfsonmicro.com, lrg@ti.com, linux-arm-kernel@lists.infradead.org, w.sang@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sun, 21 Aug 2011 15:51:35 +0000 (UTC) 1. add different clkmux mode handling for record. SAIF can use two instances to implement full duplex (playback & recording) and record saif may work on EXTMASTER mode that is using other saif's BITCLK&LRCLK. The clkmux mode is determined by saif's platform data and machine specific clkmux setting is done in pdata->init(). 2. support playback and capture simutaneously however the sample rates can not be different due to hw limitation. Signed-off-by: Dong Aisheng Cc: Mark Brown Cc: Liam Girdwood Cc: Sascha Hauer Cc: Wolfram Sang --- include/sound/saif.h | 16 +++++ sound/soc/mxs/mxs-saif.c | 162 ++++++++++++++++++++++++++++++++++++++++++---- sound/soc/mxs/mxs-saif.h | 4 + 3 files changed, 168 insertions(+), 14 deletions(-) diff --git a/include/sound/saif.h b/include/sound/saif.h new file mode 100644 index 0000000..7a98d9b --- /dev/null +++ b/include/sound/saif.h @@ -0,0 +1,16 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MXS_SAIF_H__ +#define __MACH_MXS_SAIF_H__ + +struct mxs_saif_platform_data { + unsigned int clkmux; + int (*init) (void); +}; +#endif diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c index 530017f..eb8ba79 100644 --- a/sound/soc/mxs/mxs-saif.c +++ b/sound/soc/mxs/mxs-saif.c @@ -27,15 +27,39 @@ #include #include #include +#include #include #include #include #include +#include #include "mxs-saif.h" static struct mxs_saif *mxs_saif[2]; +/* + * SAIF is a little different with other normal SOC DAIs on clock using. + * + * For MXS, two SAIF modules are instantiated on-chip. + * Each SAIF has a set of clock pins and can be operating in master + * mode simultaneously if they are connected to different off-chip codecs. + * Also, one of the two SAIFs can master or drive the clock pins while the + * other SAIF, in slave mode, receives clocking from the master SAIF. + * This also means that both SAIFs must operate at the same sample rate. + * Following are the valid configurations for SAIF1 and SAIF2 on the i.MX28 + * + * HW_SAIF_CLKMUX_SEL: + * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1 + * clock pins selected for SAIF1 input clocks. + * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and + * SAIF0 clock inputs selected for SAIF1 input clocks. + * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input + * clocks. + * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input + * clocks. + */ + static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, unsigned int freq, int dir) { @@ -52,6 +76,36 @@ static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, } /* + * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK + * is provided by other SAIF, we provide a interface here to get its master. + * Note that for DIRECT mode, it's master is itself. + */ +static struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) +{ + struct mxs_saif *master_saif; + + /* get master saif according to different clkmux setting */ + switch (saif->clkmux) { + case MXS_DIGCTL_SAIF_CLKMUX_DIRECT: + master_saif = saif; + break; + case MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT: + master_saif = saif->id ? mxs_saif[1] : mxs_saif[0]; + break; + case MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0: + master_saif = mxs_saif[0]; + break; + case MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1: + master_saif = mxs_saif[1]; + break; + default: + return NULL; + } + + return master_saif; +} + +/* * Set SAIF clock and MCLK */ static int mxs_saif_set_clk(struct mxs_saif *saif, @@ -60,8 +114,27 @@ static int mxs_saif_set_clk(struct mxs_saif *saif, { u32 scr; int ret; + struct mxs_saif *master_saif; - scr = __raw_readl(saif->base + SAIF_CTRL); + dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); + + /* Set master saif to generate proper clock */ + master_saif = mxs_saif_get_master(saif); + if (!master_saif) + return -EINVAL; + + dev_dbg(saif->dev, "master saif%d clkmux 0x%x\n", + master_saif->id, saif->clkmux); + + /* Checking if can playback and capture simutaneously */ + if (master_saif->ongoing && rate != master_saif->cur_rate) { + dev_err(saif->dev, + "can not change clock, master saif%d(rate %d) is ongoing\n", + master_saif->id, master_saif->cur_rate); + return -EINVAL; + } + + scr = __raw_readl(master_saif->base + SAIF_CTRL); scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; @@ -75,27 +148,29 @@ static int mxs_saif_set_clk(struct mxs_saif *saif, * * If MCLK is not used, we just set saif clk to 512*fs. */ - if (saif->mclk_in_use) { + if (master_saif->mclk_in_use) { if (mclk % 32 == 0) { scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; - ret = clk_set_rate(saif->clk, 512 * rate); + ret = clk_set_rate(master_saif->clk, 512 * rate); } else if (mclk % 48 == 0) { scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; - ret = clk_set_rate(saif->clk, 384 * rate); + ret = clk_set_rate(master_saif->clk, 384 * rate); } else { /* SAIF MCLK should be either 32x or 48x */ return -EINVAL; } } else { - ret = clk_set_rate(saif->clk, 512 * rate); + ret = clk_set_rate(master_saif->clk, 512 * rate); scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; } if (ret) return ret; - if (!saif->mclk_in_use) { - __raw_writel(scr, saif->base + SAIF_CTRL); + master_saif->cur_rate = rate; + + if (!master_saif->mclk_in_use) { + __raw_writel(scr, master_saif->base + SAIF_CTRL); return 0; } @@ -137,7 +212,7 @@ static int mxs_saif_set_clk(struct mxs_saif *saif, return -EINVAL; } - __raw_writel(scr, saif->base + SAIF_CTRL); + __raw_writel(scr, master_saif->base + SAIF_CTRL); return 0; } @@ -183,6 +258,7 @@ int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, struct mxs_saif *saif = mxs_saif[saif_id]; u32 stat; int ret; + struct mxs_saif *master_saif; if (!saif) return -EINVAL; @@ -195,6 +271,12 @@ int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, __raw_writel(BM_SAIF_CTRL_CLKGATE, saif->base + SAIF_CTRL + MXS_CLR_ADDR); + master_saif = mxs_saif_get_master(saif); + if (saif != master_saif) { + dev_err(saif->dev, "can not get mclk from a non-master saif\n"); + return -EINVAL; + } + stat = __raw_readl(saif->base + SAIF_STAT); if (stat & BM_SAIF_STAT_BUSY) { dev_err(saif->dev, "error: busy\n"); @@ -278,10 +360,21 @@ static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) /* * Note: We simply just support master mode since SAIF TX can only * work as master. + * Here the master is relative to codec side. + * Saif internally could be slave when working on EXTMASTER mode. + * We just hide this to machine driver. */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: - scr &= ~BM_SAIF_CTRL_SLAVE_MODE; + if (saif->clkmux == MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0) + scr = saif->id ? scr | BM_SAIF_CTRL_SLAVE_MODE : + scr & ~BM_SAIF_CTRL_SLAVE_MODE; + else if (saif->clkmux == MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1) + scr = saif->id ? scr & ~BM_SAIF_CTRL_SLAVE_MODE : + scr | BM_SAIF_CTRL_SLAVE_MODE; + else + scr &= ~BM_SAIF_CTRL_SLAVE_MODE; + __raw_writel(scr | scr0, saif->base + SAIF_CTRL); break; default: @@ -396,6 +489,11 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *cpu_dai) { struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); + struct mxs_saif *master_saif; + + master_saif = mxs_saif_get_master(saif); + if (!master_saif) + return -EINVAL; switch (cmd) { case SNDRV_PCM_TRIGGER_START: @@ -403,10 +501,20 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: dev_dbg(cpu_dai->dev, "start\n"); - clk_enable(saif->clk); - if (!saif->mclk_in_use) + clk_enable(master_saif->clk); + if (!master_saif->mclk_in_use) + __raw_writel(BM_SAIF_CTRL_RUN, + master_saif->base + SAIF_CTRL + MXS_SET_ADDR); + + /* + * If the saif's master is not himself, we also need to enable + * itself clk for its internal basic logic to work. + */ + if (saif != master_saif) { + clk_enable(saif->clk); __raw_writel(BM_SAIF_CTRL_RUN, saif->base + SAIF_CTRL + MXS_SET_ADDR); + } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { /* @@ -422,20 +530,37 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, __raw_readl(saif->base + SAIF_DATA); } - dev_dbg(cpu_dai->dev, "CTRL 0x%x STAT 0x%x\n", + master_saif->ongoing = 1; + + dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", __raw_readl(saif->base + SAIF_CTRL), __raw_readl(saif->base + SAIF_STAT)); + dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", + __raw_readl(master_saif->base + SAIF_CTRL), + __raw_readl(master_saif->base + SAIF_STAT)); break; case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: dev_dbg(cpu_dai->dev, "stop\n"); - clk_disable(saif->clk); - if (!saif->mclk_in_use) + if (!master_saif->mclk_in_use) { + __raw_writel(BM_SAIF_CTRL_RUN, + master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); + udelay(100); + } + clk_disable(master_saif->clk); + + if (saif != master_saif) { __raw_writel(BM_SAIF_CTRL_RUN, saif->base + SAIF_CTRL + MXS_CLR_ADDR); + /* wait a while for the current sample to complete */ + udelay(100); + clk_disable(saif->clk); + } + + master_saif->ongoing = 0; break; default: @@ -519,15 +644,24 @@ static int mxs_saif_probe(struct platform_device *pdev) { struct resource *res; struct mxs_saif *saif; + struct mxs_saif_platform_data *pdata; int ret = 0; + pdata = pdev->dev.platform_data; + if (pdata && pdata->init()) + return -EINVAL; + saif = kzalloc(sizeof(*saif), GFP_KERNEL); if (!saif) return -ENOMEM; + if (pdata) + saif->clkmux = pdata->clkmux; + if (pdev->id >= ARRAY_SIZE(mxs_saif)) return -EINVAL; mxs_saif[pdev->id] = saif; + saif->id = pdev->id; saif->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(saif->clk)) { diff --git a/sound/soc/mxs/mxs-saif.h b/sound/soc/mxs/mxs-saif.h index 0e2ff8c..2a6aec1 100644 --- a/sound/soc/mxs/mxs-saif.h +++ b/sound/soc/mxs/mxs-saif.h @@ -118,6 +118,10 @@ struct mxs_saif { void __iomem *base; int irq; struct mxs_pcm_dma_params dma_param; + unsigned int id; + unsigned int clkmux; + unsigned int cur_rate; + unsigned int ongoing; struct platform_device *soc_platform_pdev; u32 fifo_underrun;