[v10,23/27] MIPS: CI20: Reduce system timer and clocksource to 3 MHz
diff mbox series

Message ID 20190302233413.14813-24-paul@crapouillou.net
State Not Applicable
Headers show
Series
  • Ingenic TCU patchset
Related show

Commit Message

Paul Cercueil March 2, 2019, 11:34 p.m. UTC
The default clock (48 MHz) is too fast for the system timer.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---

Notes:
         v5: New patch
    
         v6: Set also the rate for the clocksource channel's clock
    
         v7: No change
    
         v8: No change
    
         v9: Don't configure clock timer1, as the OS Timer is used as
             clocksource on this SoC
    
         v10: Revert back to v8 bahaviour. Let the user choose what
              clocksource should be used.

 arch/mips/boot/dts/ingenic/ci20.dts | 6 ++++++
 1 file changed, 6 insertions(+)

Patch
diff mbox series

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 4f7b1fa31cf5..30b01cfaaf5a 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -238,3 +238,9 @@ 
 		bias-disable;
 	};
 };
+
+&tcu {
+	/* 3 MHz for the system timer and clocksource */
+	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
+	assigned-clock-rates = <3000000>, <3000000>;
+};