[v5,1/9] clk: mediatek: Disable tuner_en before change PLL rate
diff mbox series

Message ID 20190305050546.23431-3-weiyi.lu@mediatek.com
State New
Headers show
Series
  • Mediatek MT8183 clock support
Related show

Commit Message

Weiyi Lu March 5, 2019, 5:05 a.m. UTC
From: Owen Chen <owen.chen@mediatek.com>

PLLs with tuner_en bit, such as APLL1, need to disable
tuner_en before apply new frequency settings, or the new frequency
settings (pcw) will not be applied.
The tuner_en bit will be disabled during changing PLL rate
and be restored after new settings applied.

Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
Cc: <stable@vger.kernel.org>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++----------
 1 file changed, 34 insertions(+), 14 deletions(-)

Comments

James Liao March 5, 2019, 6:42 a.m. UTC | #1
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: Owen Chen <owen.chen@mediatek.com>
> 
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be restored after new settings applied.
> 
> Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>

Reviewed-by: James Liao <jamesjj.liao@mediatek.com>

> ---
>  drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++----------
>  1 file changed, 34 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index f54e4015b0b1..18842d660317 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
>  	return ((unsigned long)vco + postdiv - 1) / postdiv;
>  }
>  
> +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
> +{
> +	u32 r;
> +
> +	if (pll->tuner_en_addr) {
> +		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> +		writel(r, pll->tuner_en_addr);
> +	} else if (pll->tuner_addr) {
> +		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> +		writel(r, pll->tuner_addr);
> +	}
> +}
> +
> +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
> +{
> +	u32 r;
> +
> +	if (pll->tuner_en_addr) {
> +		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> +		writel(r, pll->tuner_en_addr);
> +	} else if (pll->tuner_addr) {
> +		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> +		writel(r, pll->tuner_addr);
> +	}
> +}
> +
>  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  		int postdiv)
>  {
> @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  
>  	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
>  
> +	/* disable tuner */
> +	__mtk_pll_tuner_disable(pll);
> +
>  	/* set postdiv */
>  	val = readl(pll->pd_addr);
>  	val &= ~(POSTDIV_MASK << pll->data->pd_shift);
> @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  	if (pll->tuner_addr)
>  		writel(con1 + 1, pll->tuner_addr);
>  
> +	/* restore tuner_en */
> +	__mtk_pll_tuner_enable(pll);
> +
>  	if (pll_en)
>  		udelay(20);
>  }
> @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
>  	r |= pll->data->en_mask;
>  	writel(r, pll->base_addr + REG_CON0);
>  
> -	if (pll->tuner_en_addr) {
> -		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> -		writel(r, pll->tuner_en_addr);
> -	} else if (pll->tuner_addr) {
> -		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> -		writel(r, pll->tuner_addr);
> -	}
> +	__mtk_pll_tuner_enable(pll);
>  
>  	udelay(20);
>  
> @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
>  		writel(r, pll->base_addr + REG_CON0);
>  	}
>  
> -	if (pll->tuner_en_addr) {
> -		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> -		writel(r, pll->tuner_en_addr);
> -	} else if (pll->tuner_addr) {
> -		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> -		writel(r, pll->tuner_addr);
> -	}
> +	__mtk_pll_tuner_disable(pll);
>  
>  	r = readl(pll->base_addr + REG_CON0);
>  	r &= ~CON0_BASE_EN;
Matthias Brugger March 7, 2019, 4:09 p.m. UTC | #2
On 05/03/2019 06:05, Weiyi Lu wrote:
> From: Owen Chen <owen.chen@mediatek.com>
> 
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be restored after new settings applied.
> 
> Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

> ---
>  drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++----------
>  1 file changed, 34 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index f54e4015b0b1..18842d660317 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
>  	return ((unsigned long)vco + postdiv - 1) / postdiv;
>  }
>  
> +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
> +{
> +	u32 r;
> +
> +	if (pll->tuner_en_addr) {
> +		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> +		writel(r, pll->tuner_en_addr);
> +	} else if (pll->tuner_addr) {
> +		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> +		writel(r, pll->tuner_addr);
> +	}
> +}
> +
> +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
> +{
> +	u32 r;
> +
> +	if (pll->tuner_en_addr) {
> +		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> +		writel(r, pll->tuner_en_addr);
> +	} else if (pll->tuner_addr) {
> +		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> +		writel(r, pll->tuner_addr);
> +	}
> +}
> +
>  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  		int postdiv)
>  {
> @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  
>  	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
>  
> +	/* disable tuner */
> +	__mtk_pll_tuner_disable(pll);
> +
>  	/* set postdiv */
>  	val = readl(pll->pd_addr);
>  	val &= ~(POSTDIV_MASK << pll->data->pd_shift);
> @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  	if (pll->tuner_addr)
>  		writel(con1 + 1, pll->tuner_addr);
>  
> +	/* restore tuner_en */
> +	__mtk_pll_tuner_enable(pll);
> +
>  	if (pll_en)
>  		udelay(20);
>  }
> @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
>  	r |= pll->data->en_mask;
>  	writel(r, pll->base_addr + REG_CON0);
>  
> -	if (pll->tuner_en_addr) {
> -		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> -		writel(r, pll->tuner_en_addr);
> -	} else if (pll->tuner_addr) {
> -		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> -		writel(r, pll->tuner_addr);
> -	}
> +	__mtk_pll_tuner_enable(pll);
>  
>  	udelay(20);
>  
> @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
>  		writel(r, pll->base_addr + REG_CON0);
>  	}
>  
> -	if (pll->tuner_en_addr) {
> -		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> -		writel(r, pll->tuner_en_addr);
> -	} else if (pll->tuner_addr) {
> -		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> -		writel(r, pll->tuner_addr);
> -	}
> +	__mtk_pll_tuner_disable(pll);
>  
>  	r = readl(pll->base_addr + REG_CON0);
>  	r &= ~CON0_BASE_EN;
>
Stephen Boyd April 11, 2019, 8:16 p.m. UTC | #3
Quoting Weiyi Lu (2019-03-04 21:05:38)
> From: Owen Chen <owen.chen@mediatek.com>
> 
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be restored after new settings applied.
> 
> Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Owen Chen <owen.chen@mediatek.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---

Applied to clk-next

Patch
diff mbox series

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index f54e4015b0b1..18842d660317 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -88,6 +88,32 @@  static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
 	return ((unsigned long)vco + postdiv - 1) / postdiv;
 }
 
+static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
+{
+	u32 r;
+
+	if (pll->tuner_en_addr) {
+		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
+		writel(r, pll->tuner_en_addr);
+	} else if (pll->tuner_addr) {
+		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
+		writel(r, pll->tuner_addr);
+	}
+}
+
+static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
+{
+	u32 r;
+
+	if (pll->tuner_en_addr) {
+		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
+		writel(r, pll->tuner_en_addr);
+	} else if (pll->tuner_addr) {
+		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
+		writel(r, pll->tuner_addr);
+	}
+}
+
 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 		int postdiv)
 {
@@ -96,6 +122,9 @@  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 
 	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
 
+	/* disable tuner */
+	__mtk_pll_tuner_disable(pll);
+
 	/* set postdiv */
 	val = readl(pll->pd_addr);
 	val &= ~(POSTDIV_MASK << pll->data->pd_shift);
@@ -122,6 +151,9 @@  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 	if (pll->tuner_addr)
 		writel(con1 + 1, pll->tuner_addr);
 
+	/* restore tuner_en */
+	__mtk_pll_tuner_enable(pll);
+
 	if (pll_en)
 		udelay(20);
 }
@@ -228,13 +260,7 @@  static int mtk_pll_prepare(struct clk_hw *hw)
 	r |= pll->data->en_mask;
 	writel(r, pll->base_addr + REG_CON0);
 
-	if (pll->tuner_en_addr) {
-		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
-		writel(r, pll->tuner_en_addr);
-	} else if (pll->tuner_addr) {
-		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
-		writel(r, pll->tuner_addr);
-	}
+	__mtk_pll_tuner_enable(pll);
 
 	udelay(20);
 
@@ -258,13 +284,7 @@  static void mtk_pll_unprepare(struct clk_hw *hw)
 		writel(r, pll->base_addr + REG_CON0);
 	}
 
-	if (pll->tuner_en_addr) {
-		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
-		writel(r, pll->tuner_en_addr);
-	} else if (pll->tuner_addr) {
-		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
-		writel(r, pll->tuner_addr);
-	}
+	__mtk_pll_tuner_disable(pll);
 
 	r = readl(pll->base_addr + REG_CON0);
 	r &= ~CON0_BASE_EN;