[1/2,RFC] ata: ahci: Respect bus DMA constraints
diff mbox series

Message ID 20190307000440.8708-1-marek.vasut@gmail.com
State Under Review
Delegated to: Geert Uytterhoeven
Headers show
Series
  • [1/2,RFC] ata: ahci: Respect bus DMA constraints
Related show

Commit Message

Marek Vasut March 7, 2019, 12:04 a.m. UTC
From: Marek Vasut <marek.vasut+renesas@gmail.com>

Since commit 6c2fb2ea7636 ("of/device: Set bus DMA mask as appropriate"),
the upstream bus can constraint device DMA range. Respect that constraint
and do not change the device DMA masks if they were already set.

This is applicable e.g. on systems where the PCIe controller cannot expose
the full address space range. Such a system may have a 64bit CPU with DRAM
mapped both below and above the 32bit address space, yet the PCIe devices
can not perform DMA directly to/from the DRAM range above the 32bit limit.
Hence, for such setup to work, all the buffers must exist below the 32bit
limit.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Jens Axboe <axboe@fb.com>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Keith Busch <keith.busch@intel.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Sagi Grimberg <sagi@grimberg.me>
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
Cc: linux-renesas-soc@vger.kernel.org
To: linux-ide@vger.kernel.org
To: linux-nvme@lists.infradead.org
---
 drivers/ata/ahci.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Robin Murphy March 7, 2019, 9:32 a.m. UTC | #1
On 2019-03-07 12:04 am, marek.vasut@gmail.com wrote:
> From: Marek Vasut <marek.vasut+renesas@gmail.com>
> 
> Since commit 6c2fb2ea7636 ("of/device: Set bus DMA mask as appropriate"),
> the upstream bus can constraint device DMA range. Respect that constraint
> and do not change the device DMA masks if they were already set.
> 
> This is applicable e.g. on systems where the PCIe controller cannot expose
> the full address space range. Such a system may have a 64bit CPU with DRAM
> mapped both below and above the 32bit address space, yet the PCIe devices
> can not perform DMA directly to/from the DRAM range above the 32bit limit.
> Hence, for such setup to work, all the buffers must exist below the 32bit
> limit.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Christoph Hellwig <hch@lst.de>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Jens Axboe <axboe@fb.com>
> Cc: Jens Axboe <axboe@kernel.dk>
> Cc: Keith Busch <keith.busch@intel.com>
> Cc: Robin Murphy <robin.murphy@arm.com>
> Cc: Sagi Grimberg <sagi@grimberg.me>
> Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Cc: linux-renesas-soc@vger.kernel.org
> To: linux-ide@vger.kernel.org
> To: linux-nvme@lists.infradead.org
> ---
>   drivers/ata/ahci.c | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> index 021ce46e2e57..2acce056dd8c 100644
> --- a/drivers/ata/ahci.c
> +++ b/drivers/ata/ahci.c
> @@ -926,6 +926,13 @@ static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
>   	if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
>   		return 0;
>   
> +	/*
> +	 * The upstream device could have applied DMA constraints already,
> +	 * respect those and do not change the DMA masks.
> +	 */
> +	if (pdev->dev.dma_mask && pdev->dev.coherent_dma_mask)
> +		return 0;

At least for DT platforms, the device masks are always going to be set 
to some initial value, which will most commonly just be the 32-bit 
default - that should not prevent the driver from setting wider masks if 
that's what the device really supports (in fact there are some patches 
queued in which we're now starting to formalise that properly).

Are you seeing a problem with a DMA API backend failing to respect 
bus_dma_mask?

Robin.

> +
>   	if (using_dac &&
>   	    !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
>   		rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
>
Marek Vasut March 7, 2019, 9:37 a.m. UTC | #2
On 3/7/19 10:32 AM, Robin Murphy wrote:
> On 2019-03-07 12:04 am, marek.vasut@gmail.com wrote:
>> From: Marek Vasut <marek.vasut+renesas@gmail.com>
>>
>> Since commit 6c2fb2ea7636 ("of/device: Set bus DMA mask as appropriate"),
>> the upstream bus can constraint device DMA range. Respect that constraint
>> and do not change the device DMA masks if they were already set.
>>
>> This is applicable e.g. on systems where the PCIe controller cannot
>> expose
>> the full address space range. Such a system may have a 64bit CPU with
>> DRAM
>> mapped both below and above the 32bit address space, yet the PCIe devices
>> can not perform DMA directly to/from the DRAM range above the 32bit
>> limit.
>> Hence, for such setup to work, all the buffers must exist below the 32bit
>> limit.
>>
>> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
>> Cc: Christoph Hellwig <hch@lst.de>
>> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
>> Cc: Jens Axboe <axboe@fb.com>
>> Cc: Jens Axboe <axboe@kernel.dk>
>> Cc: Keith Busch <keith.busch@intel.com>
>> Cc: Robin Murphy <robin.murphy@arm.com>
>> Cc: Sagi Grimberg <sagi@grimberg.me>
>> Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
>> Cc: linux-renesas-soc@vger.kernel.org
>> To: linux-ide@vger.kernel.org
>> To: linux-nvme@lists.infradead.org
>> ---
>>   drivers/ata/ahci.c | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
>> index 021ce46e2e57..2acce056dd8c 100644
>> --- a/drivers/ata/ahci.c
>> +++ b/drivers/ata/ahci.c
>> @@ -926,6 +926,13 @@ static int ahci_configure_dma_masks(struct
>> pci_dev *pdev, int using_dac)
>>       if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
>>           return 0;
>>   +    /*
>> +     * The upstream device could have applied DMA constraints already,
>> +     * respect those and do not change the DMA masks.
>> +     */
>> +    if (pdev->dev.dma_mask && pdev->dev.coherent_dma_mask)
>> +        return 0;
> 
> At least for DT platforms, the device masks are always going to be set
> to some initial value, which will most commonly just be the 32-bit
> default - that should not prevent the driver from setting wider masks if
> that's what the device really supports (in fact there are some patches
> queued in which we're now starting to formalise that properly).
> 
> Are you seeing a problem with a DMA API backend failing to respect
> bus_dma_mask?

Yes, the DMA mask gets overridden here to 64bit one, which on the R-Car
Gen3 with PCI with 32bit addressing limitation makes the AHCI driver
fail (and NVMe driver, and xHCI PCI etc). All those PCI devices fail the
same way because they override the DMA mask.
Robin Murphy March 7, 2019, 9:48 a.m. UTC | #3
On 2019-03-07 9:37 am, Marek Vasut wrote:
> On 3/7/19 10:32 AM, Robin Murphy wrote:
>> On 2019-03-07 12:04 am, marek.vasut@gmail.com wrote:
>>> From: Marek Vasut <marek.vasut+renesas@gmail.com>
>>>
>>> Since commit 6c2fb2ea7636 ("of/device: Set bus DMA mask as appropriate"),
>>> the upstream bus can constraint device DMA range. Respect that constraint
>>> and do not change the device DMA masks if they were already set.
>>>
>>> This is applicable e.g. on systems where the PCIe controller cannot
>>> expose
>>> the full address space range. Such a system may have a 64bit CPU with
>>> DRAM
>>> mapped both below and above the 32bit address space, yet the PCIe devices
>>> can not perform DMA directly to/from the DRAM range above the 32bit
>>> limit.
>>> Hence, for such setup to work, all the buffers must exist below the 32bit
>>> limit.
>>>
>>> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
>>> Cc: Christoph Hellwig <hch@lst.de>
>>> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
>>> Cc: Jens Axboe <axboe@fb.com>
>>> Cc: Jens Axboe <axboe@kernel.dk>
>>> Cc: Keith Busch <keith.busch@intel.com>
>>> Cc: Robin Murphy <robin.murphy@arm.com>
>>> Cc: Sagi Grimberg <sagi@grimberg.me>
>>> Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
>>> Cc: linux-renesas-soc@vger.kernel.org
>>> To: linux-ide@vger.kernel.org
>>> To: linux-nvme@lists.infradead.org
>>> ---
>>>    drivers/ata/ahci.c | 7 +++++++
>>>    1 file changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
>>> index 021ce46e2e57..2acce056dd8c 100644
>>> --- a/drivers/ata/ahci.c
>>> +++ b/drivers/ata/ahci.c
>>> @@ -926,6 +926,13 @@ static int ahci_configure_dma_masks(struct
>>> pci_dev *pdev, int using_dac)
>>>        if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
>>>            return 0;
>>>    +    /*
>>> +     * The upstream device could have applied DMA constraints already,
>>> +     * respect those and do not change the DMA masks.
>>> +     */
>>> +    if (pdev->dev.dma_mask && pdev->dev.coherent_dma_mask)
>>> +        return 0;
>>
>> At least for DT platforms, the device masks are always going to be set
>> to some initial value, which will most commonly just be the 32-bit
>> default - that should not prevent the driver from setting wider masks if
>> that's what the device really supports (in fact there are some patches
>> queued in which we're now starting to formalise that properly).
>>
>> Are you seeing a problem with a DMA API backend failing to respect
>> bus_dma_mask?
> 
> Yes, the DMA mask gets overridden here to 64bit one, which on the R-Car
> Gen3 with PCI with 32bit addressing limitation makes the AHCI driver
> fail (and NVMe driver, and xHCI PCI etc). All those PCI devices fail the
> same way because they override the DMA mask.

Right, but whoever *interprets* the device masks after the driver has 
overridden them should be taking the (smaller) bus mask into account as 
well, so the question is where is *that* not being done correctly?

Robin.
Marek Vasut March 7, 2019, 11:14 a.m. UTC | #4
On 3/7/19 10:48 AM, Robin Murphy wrote:
> On 2019-03-07 9:37 am, Marek Vasut wrote:
>> On 3/7/19 10:32 AM, Robin Murphy wrote:
>>> On 2019-03-07 12:04 am, marek.vasut@gmail.com wrote:
>>>> From: Marek Vasut <marek.vasut+renesas@gmail.com>
>>>>
>>>> Since commit 6c2fb2ea7636 ("of/device: Set bus DMA mask as
>>>> appropriate"),
>>>> the upstream bus can constraint device DMA range. Respect that
>>>> constraint
>>>> and do not change the device DMA masks if they were already set.
>>>>
>>>> This is applicable e.g. on systems where the PCIe controller cannot
>>>> expose
>>>> the full address space range. Such a system may have a 64bit CPU with
>>>> DRAM
>>>> mapped both below and above the 32bit address space, yet the PCIe
>>>> devices
>>>> can not perform DMA directly to/from the DRAM range above the 32bit
>>>> limit.
>>>> Hence, for such setup to work, all the buffers must exist below the
>>>> 32bit
>>>> limit.
>>>>
>>>> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
>>>> Cc: Christoph Hellwig <hch@lst.de>
>>>> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
>>>> Cc: Jens Axboe <axboe@fb.com>
>>>> Cc: Jens Axboe <axboe@kernel.dk>
>>>> Cc: Keith Busch <keith.busch@intel.com>
>>>> Cc: Robin Murphy <robin.murphy@arm.com>
>>>> Cc: Sagi Grimberg <sagi@grimberg.me>
>>>> Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
>>>> Cc: linux-renesas-soc@vger.kernel.org
>>>> To: linux-ide@vger.kernel.org
>>>> To: linux-nvme@lists.infradead.org
>>>> ---
>>>>    drivers/ata/ahci.c | 7 +++++++
>>>>    1 file changed, 7 insertions(+)
>>>>
>>>> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
>>>> index 021ce46e2e57..2acce056dd8c 100644
>>>> --- a/drivers/ata/ahci.c
>>>> +++ b/drivers/ata/ahci.c
>>>> @@ -926,6 +926,13 @@ static int ahci_configure_dma_masks(struct
>>>> pci_dev *pdev, int using_dac)
>>>>        if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
>>>>            return 0;
>>>>    +    /*
>>>> +     * The upstream device could have applied DMA constraints already,
>>>> +     * respect those and do not change the DMA masks.
>>>> +     */
>>>> +    if (pdev->dev.dma_mask && pdev->dev.coherent_dma_mask)
>>>> +        return 0;
>>>
>>> At least for DT platforms, the device masks are always going to be set
>>> to some initial value, which will most commonly just be the 32-bit
>>> default - that should not prevent the driver from setting wider masks if
>>> that's what the device really supports (in fact there are some patches
>>> queued in which we're now starting to formalise that properly).
>>>
>>> Are you seeing a problem with a DMA API backend failing to respect
>>> bus_dma_mask?
>>
>> Yes, the DMA mask gets overridden here to 64bit one, which on the R-Car
>> Gen3 with PCI with 32bit addressing limitation makes the AHCI driver
>> fail (and NVMe driver, and xHCI PCI etc). All those PCI devices fail the
>> same way because they override the DMA mask.
> 
> Right, but whoever *interprets* the device masks after the driver has
> overridden them should be taking the (smaller) bus mask into account as
> well, so the question is where is *that* not being done correctly?

Do you have a hint where I should look for that ?
Christoph Hellwig March 8, 2019, 7:18 a.m. UTC | #5
On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
> > Right, but whoever *interprets* the device masks after the driver has
> > overridden them should be taking the (smaller) bus mask into account as
> > well, so the question is where is *that* not being done correctly?
> 
> Do you have a hint where I should look for that ?

If this a 32-bit ARM platform it might the complete lack of support
for bus_dma_mask in arch/arm/mm/dma-mapping.c..
Marek Vasut March 8, 2019, 11:23 p.m. UTC | #6
On 3/8/19 8:18 AM, Christoph Hellwig wrote:
> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
>>> Right, but whoever *interprets* the device masks after the driver has
>>> overridden them should be taking the (smaller) bus mask into account as
>>> well, so the question is where is *that* not being done correctly?
>>
>> Do you have a hint where I should look for that ?
> 
> If this a 32-bit ARM platform it might the complete lack of support
> for bus_dma_mask in arch/arm/mm/dma-mapping.c..

It's an ARM 64bit platform, just the PCIe controller is limited to 32bit
address range, so the devices on the PCIe bus cannot read the host's
DRAM above the 32bit limit.
Christoph Hellwig March 13, 2019, 6:30 p.m. UTC | #7
On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
> > On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
> >>> Right, but whoever *interprets* the device masks after the driver has
> >>> overridden them should be taking the (smaller) bus mask into account as
> >>> well, so the question is where is *that* not being done correctly?
> >>
> >> Do you have a hint where I should look for that ?
> > 
> > If this a 32-bit ARM platform it might the complete lack of support
> > for bus_dma_mask in arch/arm/mm/dma-mapping.c..
> 
> It's an ARM 64bit platform, just the PCIe controller is limited to 32bit
> address range, so the devices on the PCIe bus cannot read the host's
> DRAM above the 32bit limit.

arm64 should take the mask into account both for the swiotlb and
iommu case.  What are the exact symptoms you see?  Does it involve
swiotlb not kicking in, or iommu issues?  What is the exact kernel
version?
Marek Vasut March 16, 2019, 9:25 p.m. UTC | #8
On 3/13/19 7:30 PM, Christoph Hellwig wrote:
> On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
>> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
>>> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
>>>>> Right, but whoever *interprets* the device masks after the driver has
>>>>> overridden them should be taking the (smaller) bus mask into account as
>>>>> well, so the question is where is *that* not being done correctly?
>>>>
>>>> Do you have a hint where I should look for that ?
>>>
>>> If this a 32-bit ARM platform it might the complete lack of support
>>> for bus_dma_mask in arch/arm/mm/dma-mapping.c..
>>
>> It's an ARM 64bit platform, just the PCIe controller is limited to 32bit
>> address range, so the devices on the PCIe bus cannot read the host's
>> DRAM above the 32bit limit.
> 
> arm64 should take the mask into account both for the swiotlb and
> iommu case.  What are the exact symptoms you see?

With the nvme, the device is recognized, but cannot be used.
It boils down to PCI BAR access being possible, since that's all below
the 32bit boundary, but when the device tries to do any sort of DMA,
that transfer returns nonsense data.

But when I call dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32) in
the affected driver (thus far I tried this nvme, xhci-pci and ahci-pci
drivers), it all starts to work fine.

Could it be that the driver overwrites the (coherent_)dma_mask and
that's why the swiotlb/iommu code cannot take this into account ?

> Does it involve
> swiotlb not kicking in, or iommu issues?

How can I check ? I added printks into arch/arm64/mm/dma-mapping.c and
drivers/iommu/dma-iommu.c , but I suspect I need to look elsewhere.

> What is the exact kernel version?

next/master from 20190306 (5.0.0 + next patches)
Marek Vasut March 16, 2019, 11:04 p.m. UTC | #9
On 3/16/19 10:25 PM, Marek Vasut wrote:
> On 3/13/19 7:30 PM, Christoph Hellwig wrote:
>> On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
>>> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
>>>> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
>>>>>> Right, but whoever *interprets* the device masks after the driver has
>>>>>> overridden them should be taking the (smaller) bus mask into account as
>>>>>> well, so the question is where is *that* not being done correctly?
>>>>>
>>>>> Do you have a hint where I should look for that ?
>>>>
>>>> If this a 32-bit ARM platform it might the complete lack of support
>>>> for bus_dma_mask in arch/arm/mm/dma-mapping.c..
>>>
>>> It's an ARM 64bit platform, just the PCIe controller is limited to 32bit
>>> address range, so the devices on the PCIe bus cannot read the host's
>>> DRAM above the 32bit limit.
>>
>> arm64 should take the mask into account both for the swiotlb and
>> iommu case.  What are the exact symptoms you see?
> 
> With the nvme, the device is recognized, but cannot be used.
> It boils down to PCI BAR access being possible, since that's all below
> the 32bit boundary, but when the device tries to do any sort of DMA,
> that transfer returns nonsense data.
> 
> But when I call dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32) in
> the affected driver (thus far I tried this nvme, xhci-pci and ahci-pci
> drivers), it all starts to work fine.
> 
> Could it be that the driver overwrites the (coherent_)dma_mask and
> that's why the swiotlb/iommu code cannot take this into account ?
> 
>> Does it involve
>> swiotlb not kicking in, or iommu issues?
> 
> How can I check ? I added printks into arch/arm64/mm/dma-mapping.c and
> drivers/iommu/dma-iommu.c , but I suspect I need to look elsewhere.

Digging further ...

drivers/nvme/host/pci.c nvme_map_data() calls dma_map_sg_attrs() and the
resulting sglist contains entry with >32bit PA. This is because
dma_map_sg_attrs() calls dma_direct_map_sg(), which in turn calls
dma_direct_map_sg(), then dma_direct_map_page() and that's where it goes
weird.

dma_direct_map_page() does a dma_direct_possible() check before
triggering swiotlb_map(). The check succeeds, so the later isn't executed.

dma_direct_possible() calls dma_capable() with dev->dma_mask =
DMA_BIT_MASK(64) and dev->dma_bus_mask = 0, so
min_not_zero(*dev->dma_mask, dev->bus_dma_mask) returns DMA_BIT_MASK(64).

Surely enough, if I hack dma_direct_possible() to return 0,
swiotlb_map() kicks in and the nvme driver starts working fine.

I presume the question here is, why is dev->bus_dma_mask = 0 ?
Geert Uytterhoeven March 17, 2019, 10:24 a.m. UTC | #10
Hi Marek,

On Sat, Mar 16, 2019 at 10:26 PM Marek Vasut <marek.vasut@gmail.com> wrote:
> On 3/13/19 7:30 PM, Christoph Hellwig wrote:
> > On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
> >> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
> >>> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
> >>>>> Right, but whoever *interprets* the device masks after the driver has
> >>>>> overridden them should be taking the (smaller) bus mask into account as
> >>>>> well, so the question is where is *that* not being done correctly?
> >>>>
> >>>> Do you have a hint where I should look for that ?
> >>>
> >>> If this a 32-bit ARM platform it might the complete lack of support
> >>> for bus_dma_mask in arch/arm/mm/dma-mapping.c..
> >>
> >> It's an ARM 64bit platform, just the PCIe controller is limited to 32bit
> >> address range, so the devices on the PCIe bus cannot read the host's
> >> DRAM above the 32bit limit.
> >
> > arm64 should take the mask into account both for the swiotlb and
> > iommu case.  What are the exact symptoms you see?
>
> With the nvme, the device is recognized, but cannot be used.
> It boils down to PCI BAR access being possible, since that's all below
> the 32bit boundary, but when the device tries to do any sort of DMA,
> that transfer returns nonsense data.
>
> But when I call dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32) in
> the affected driver (thus far I tried this nvme, xhci-pci and ahci-pci
> drivers), it all starts to work fine.
>
> Could it be that the driver overwrites the (coherent_)dma_mask and
> that's why the swiotlb/iommu code cannot take this into account ?
>
> > Does it involve
> > swiotlb not kicking in, or iommu issues?
>
> How can I check ? I added printks into arch/arm64/mm/dma-mapping.c and
> drivers/iommu/dma-iommu.c , but I suspect I need to look elsewhere.

So far the IOMMU is disabled in upstream, as no devices are whitelisted
in drivers/iommu/ipmmu-vmsa.c.

Gr{oetje,eeting}s,

                        Geert
Geert Uytterhoeven March 17, 2019, 10:29 a.m. UTC | #11
Hi Marek,

On Sun, Mar 17, 2019 at 12:04 AM Marek Vasut <marek.vasut@gmail.com> wrote:
> On 3/16/19 10:25 PM, Marek Vasut wrote:
> > On 3/13/19 7:30 PM, Christoph Hellwig wrote:
> >> On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
> >>> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
> >>>> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
> >>>>>> Right, but whoever *interprets* the device masks after the driver has
> >>>>>> overridden them should be taking the (smaller) bus mask into account as
> >>>>>> well, so the question is where is *that* not being done correctly?
> >>>>>
> >>>>> Do you have a hint where I should look for that ?
> >>>>
> >>>> If this a 32-bit ARM platform it might the complete lack of support
> >>>> for bus_dma_mask in arch/arm/mm/dma-mapping.c..
> >>>
> >>> It's an ARM 64bit platform, just the PCIe controller is limited to 32bit
> >>> address range, so the devices on the PCIe bus cannot read the host's
> >>> DRAM above the 32bit limit.
> >>
> >> arm64 should take the mask into account both for the swiotlb and
> >> iommu case.  What are the exact symptoms you see?
> >
> > With the nvme, the device is recognized, but cannot be used.
> > It boils down to PCI BAR access being possible, since that's all below
> > the 32bit boundary, but when the device tries to do any sort of DMA,
> > that transfer returns nonsense data.
> >
> > But when I call dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32) in
> > the affected driver (thus far I tried this nvme, xhci-pci and ahci-pci
> > drivers), it all starts to work fine.
> >
> > Could it be that the driver overwrites the (coherent_)dma_mask and
> > that's why the swiotlb/iommu code cannot take this into account ?
> >
> >> Does it involve
> >> swiotlb not kicking in, or iommu issues?
> >
> > How can I check ? I added printks into arch/arm64/mm/dma-mapping.c and
> > drivers/iommu/dma-iommu.c , but I suspect I need to look elsewhere.
>
> Digging further ...
>
> drivers/nvme/host/pci.c nvme_map_data() calls dma_map_sg_attrs() and the
> resulting sglist contains entry with >32bit PA. This is because
> dma_map_sg_attrs() calls dma_direct_map_sg(), which in turn calls
> dma_direct_map_sg(), then dma_direct_map_page() and that's where it goes
> weird.
>
> dma_direct_map_page() does a dma_direct_possible() check before
> triggering swiotlb_map(). The check succeeds, so the later isn't executed.
>
> dma_direct_possible() calls dma_capable() with dev->dma_mask =
> DMA_BIT_MASK(64) and dev->dma_bus_mask = 0, so
> min_not_zero(*dev->dma_mask, dev->bus_dma_mask) returns DMA_BIT_MASK(64).
>
> Surely enough, if I hack dma_direct_possible() to return 0,
> swiotlb_map() kicks in and the nvme driver starts working fine.
>
> I presume the question here is, why is dev->bus_dma_mask = 0 ?

Because that's the default, and almost no code overrides that?

$ git grep "\<bus_dma_mask ="
arch/mips/pci/fixup-sb1250.c:           dev->dev.bus_dma_mask =
DMA_BIT_MASK(32);
arch/x86/kernel/pci-dma.c:      pdev->dev.bus_dma_mask = DMA_BIT_MASK(32);
drivers/acpi/arm64/iort.c:              dev->bus_dma_mask = mask;
drivers/of/device.c:            dev->bus_dma_mask = mask;

dev is the nvme PCI device, I assume? So you can ignore the last match.

The first two seem to be related to platforms that cannot do >32 bit DMA
on PCI. So that's a hint on how to fix this...

Gr{oetje,eeting}s,

                        Geert
Marek Vasut March 17, 2019, 11:36 p.m. UTC | #12
On 3/17/19 11:29 AM, Geert Uytterhoeven wrote:
> Hi Marek,

Hi,

> On Sun, Mar 17, 2019 at 12:04 AM Marek Vasut <marek.vasut@gmail.com> wrote:
>> On 3/16/19 10:25 PM, Marek Vasut wrote:
>>> On 3/13/19 7:30 PM, Christoph Hellwig wrote:
>>>> On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
>>>>> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
>>>>>> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
>>>>>>>> Right, but whoever *interprets* the device masks after the driver has
>>>>>>>> overridden them should be taking the (smaller) bus mask into account as
>>>>>>>> well, so the question is where is *that* not being done correctly?
>>>>>>>
>>>>>>> Do you have a hint where I should look for that ?
>>>>>>
>>>>>> If this a 32-bit ARM platform it might the complete lack of support
>>>>>> for bus_dma_mask in arch/arm/mm/dma-mapping.c..
>>>>>
>>>>> It's an ARM 64bit platform, just the PCIe controller is limited to 32bit
>>>>> address range, so the devices on the PCIe bus cannot read the host's
>>>>> DRAM above the 32bit limit.
>>>>
>>>> arm64 should take the mask into account both for the swiotlb and
>>>> iommu case.  What are the exact symptoms you see?
>>>
>>> With the nvme, the device is recognized, but cannot be used.
>>> It boils down to PCI BAR access being possible, since that's all below
>>> the 32bit boundary, but when the device tries to do any sort of DMA,
>>> that transfer returns nonsense data.
>>>
>>> But when I call dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32) in
>>> the affected driver (thus far I tried this nvme, xhci-pci and ahci-pci
>>> drivers), it all starts to work fine.
>>>
>>> Could it be that the driver overwrites the (coherent_)dma_mask and
>>> that's why the swiotlb/iommu code cannot take this into account ?
>>>
>>>> Does it involve
>>>> swiotlb not kicking in, or iommu issues?
>>>
>>> How can I check ? I added printks into arch/arm64/mm/dma-mapping.c and
>>> drivers/iommu/dma-iommu.c , but I suspect I need to look elsewhere.
>>
>> Digging further ...
>>
>> drivers/nvme/host/pci.c nvme_map_data() calls dma_map_sg_attrs() and the
>> resulting sglist contains entry with >32bit PA. This is because
>> dma_map_sg_attrs() calls dma_direct_map_sg(), which in turn calls
>> dma_direct_map_sg(), then dma_direct_map_page() and that's where it goes
>> weird.
>>
>> dma_direct_map_page() does a dma_direct_possible() check before
>> triggering swiotlb_map(). The check succeeds, so the later isn't executed.
>>
>> dma_direct_possible() calls dma_capable() with dev->dma_mask =
>> DMA_BIT_MASK(64) and dev->dma_bus_mask = 0, so
>> min_not_zero(*dev->dma_mask, dev->bus_dma_mask) returns DMA_BIT_MASK(64).
>>
>> Surely enough, if I hack dma_direct_possible() to return 0,
>> swiotlb_map() kicks in and the nvme driver starts working fine.
>>
>> I presume the question here is, why is dev->bus_dma_mask = 0 ?
> 
> Because that's the default, and almost no code overrides that?

But shouldn't drivers/of/device.c set that for the PCIe controller ?

> $ git grep "\<bus_dma_mask ="
> arch/mips/pci/fixup-sb1250.c:           dev->dev.bus_dma_mask =
> DMA_BIT_MASK(32);
> arch/x86/kernel/pci-dma.c:      pdev->dev.bus_dma_mask = DMA_BIT_MASK(32);
> drivers/acpi/arm64/iort.c:              dev->bus_dma_mask = mask;
> drivers/of/device.c:            dev->bus_dma_mask = mask;
> 
> dev is the nvme PCI device, I assume? So you can ignore the last match.
> 
> The first two seem to be related to platforms that cannot do >32 bit DMA
> on PCI. So that's a hint on how to fix this...

That doesn't feel right, it's not a platform limitation, but a PCIe IP
limitation, so this fix should live somewhere in drivers/ I think ?
Robin Murphy March 18, 2019, 1:14 p.m. UTC | #13
On 17/03/2019 23:36, Marek Vasut wrote:
> On 3/17/19 11:29 AM, Geert Uytterhoeven wrote:
>> Hi Marek,
> 
> Hi,
> 
>> On Sun, Mar 17, 2019 at 12:04 AM Marek Vasut <marek.vasut@gmail.com> wrote:
>>> On 3/16/19 10:25 PM, Marek Vasut wrote:
>>>> On 3/13/19 7:30 PM, Christoph Hellwig wrote:
>>>>> On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
>>>>>> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
>>>>>>> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
>>>>>>>>> Right, but whoever *interprets* the device masks after the driver has
>>>>>>>>> overridden them should be taking the (smaller) bus mask into account as
>>>>>>>>> well, so the question is where is *that* not being done correctly?
>>>>>>>>
>>>>>>>> Do you have a hint where I should look for that ?
>>>>>>>
>>>>>>> If this a 32-bit ARM platform it might the complete lack of support
>>>>>>> for bus_dma_mask in arch/arm/mm/dma-mapping.c..
>>>>>>
>>>>>> It's an ARM 64bit platform, just the PCIe controller is limited to 32bit
>>>>>> address range, so the devices on the PCIe bus cannot read the host's
>>>>>> DRAM above the 32bit limit.
>>>>>
>>>>> arm64 should take the mask into account both for the swiotlb and
>>>>> iommu case.  What are the exact symptoms you see?
>>>>
>>>> With the nvme, the device is recognized, but cannot be used.
>>>> It boils down to PCI BAR access being possible, since that's all below
>>>> the 32bit boundary, but when the device tries to do any sort of DMA,
>>>> that transfer returns nonsense data.
>>>>
>>>> But when I call dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32) in
>>>> the affected driver (thus far I tried this nvme, xhci-pci and ahci-pci
>>>> drivers), it all starts to work fine.
>>>>
>>>> Could it be that the driver overwrites the (coherent_)dma_mask and
>>>> that's why the swiotlb/iommu code cannot take this into account ?
>>>>
>>>>> Does it involve
>>>>> swiotlb not kicking in, or iommu issues?
>>>>
>>>> How can I check ? I added printks into arch/arm64/mm/dma-mapping.c and
>>>> drivers/iommu/dma-iommu.c , but I suspect I need to look elsewhere.
>>>
>>> Digging further ...
>>>
>>> drivers/nvme/host/pci.c nvme_map_data() calls dma_map_sg_attrs() and the
>>> resulting sglist contains entry with >32bit PA. This is because
>>> dma_map_sg_attrs() calls dma_direct_map_sg(), which in turn calls
>>> dma_direct_map_sg(), then dma_direct_map_page() and that's where it goes
>>> weird.
>>>
>>> dma_direct_map_page() does a dma_direct_possible() check before
>>> triggering swiotlb_map(). The check succeeds, so the later isn't executed.
>>>
>>> dma_direct_possible() calls dma_capable() with dev->dma_mask =
>>> DMA_BIT_MASK(64) and dev->dma_bus_mask = 0, so
>>> min_not_zero(*dev->dma_mask, dev->bus_dma_mask) returns DMA_BIT_MASK(64).
>>>
>>> Surely enough, if I hack dma_direct_possible() to return 0,
>>> swiotlb_map() kicks in and the nvme driver starts working fine.
>>>
>>> I presume the question here is, why is dev->bus_dma_mask = 0 ?
>>
>> Because that's the default, and almost no code overrides that?
> 
> But shouldn't drivers/of/device.c set that for the PCIe controller ?

Urgh, I really should have spotted the significance of "NVMe", but 
somehow it failed to click :(

Of course the existing code works fine for everything *except* PCI 
devices on DT-based systems... That's because of_dma_get_range() has 
never been made to work correctly with the trick we play of passing the 
host bridge of_node through of_dma_configure(). I've got at least 2 or 3 
half-finished attempts at improving that, but they keep getting 
sidetracked into trying to clean up the various new of_dma_configure() 
hacks I find in drivers and/or falling down the rabbit-hole of starting 
to redesign the whole dma_pfn_offset machinery entirely. Let me dig one 
up and try to constrain it to solve just this most common "one single 
limited range" condition for the sake of making actual progress...

Robin.

>> $ git grep "\<bus_dma_mask ="
>> arch/mips/pci/fixup-sb1250.c:           dev->dev.bus_dma_mask =
>> DMA_BIT_MASK(32);
>> arch/x86/kernel/pci-dma.c:      pdev->dev.bus_dma_mask = DMA_BIT_MASK(32);
>> drivers/acpi/arm64/iort.c:              dev->bus_dma_mask = mask;
>> drivers/of/device.c:            dev->bus_dma_mask = mask;
>>
>> dev is the nvme PCI device, I assume? So you can ignore the last match.
>>
>> The first two seem to be related to platforms that cannot do >32 bit DMA
>> on PCI. So that's a hint on how to fix this...
> 
> That doesn't feel right, it's not a platform limitation, but a PCIe IP
> limitation, so this fix should live somewhere in drivers/ I think ? >
Marek Vasut March 18, 2019, 11:25 p.m. UTC | #14
On 3/18/19 2:14 PM, Robin Murphy wrote:
> On 17/03/2019 23:36, Marek Vasut wrote:
>> On 3/17/19 11:29 AM, Geert Uytterhoeven wrote:
>>> Hi Marek,
>>
>> Hi,
>>
>>> On Sun, Mar 17, 2019 at 12:04 AM Marek Vasut <marek.vasut@gmail.com>
>>> wrote:
>>>> On 3/16/19 10:25 PM, Marek Vasut wrote:
>>>>> On 3/13/19 7:30 PM, Christoph Hellwig wrote:
>>>>>> On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
>>>>>>> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
>>>>>>>> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
>>>>>>>>>> Right, but whoever *interprets* the device masks after the
>>>>>>>>>> driver has
>>>>>>>>>> overridden them should be taking the (smaller) bus mask into
>>>>>>>>>> account as
>>>>>>>>>> well, so the question is where is *that* not being done
>>>>>>>>>> correctly?
>>>>>>>>>
>>>>>>>>> Do you have a hint where I should look for that ?
>>>>>>>>
>>>>>>>> If this a 32-bit ARM platform it might the complete lack of support
>>>>>>>> for bus_dma_mask in arch/arm/mm/dma-mapping.c..
>>>>>>>
>>>>>>> It's an ARM 64bit platform, just the PCIe controller is limited
>>>>>>> to 32bit
>>>>>>> address range, so the devices on the PCIe bus cannot read the host's
>>>>>>> DRAM above the 32bit limit.
>>>>>>
>>>>>> arm64 should take the mask into account both for the swiotlb and
>>>>>> iommu case.  What are the exact symptoms you see?
>>>>>
>>>>> With the nvme, the device is recognized, but cannot be used.
>>>>> It boils down to PCI BAR access being possible, since that's all below
>>>>> the 32bit boundary, but when the device tries to do any sort of DMA,
>>>>> that transfer returns nonsense data.
>>>>>
>>>>> But when I call dma_set_mask_and_coherent(dev->dev,
>>>>> DMA_BIT_MASK(32) in
>>>>> the affected driver (thus far I tried this nvme, xhci-pci and ahci-pci
>>>>> drivers), it all starts to work fine.
>>>>>
>>>>> Could it be that the driver overwrites the (coherent_)dma_mask and
>>>>> that's why the swiotlb/iommu code cannot take this into account ?
>>>>>
>>>>>> Does it involve
>>>>>> swiotlb not kicking in, or iommu issues?
>>>>>
>>>>> How can I check ? I added printks into arch/arm64/mm/dma-mapping.c and
>>>>> drivers/iommu/dma-iommu.c , but I suspect I need to look elsewhere.
>>>>
>>>> Digging further ...
>>>>
>>>> drivers/nvme/host/pci.c nvme_map_data() calls dma_map_sg_attrs() and
>>>> the
>>>> resulting sglist contains entry with >32bit PA. This is because
>>>> dma_map_sg_attrs() calls dma_direct_map_sg(), which in turn calls
>>>> dma_direct_map_sg(), then dma_direct_map_page() and that's where it
>>>> goes
>>>> weird.
>>>>
>>>> dma_direct_map_page() does a dma_direct_possible() check before
>>>> triggering swiotlb_map(). The check succeeds, so the later isn't
>>>> executed.
>>>>
>>>> dma_direct_possible() calls dma_capable() with dev->dma_mask =
>>>> DMA_BIT_MASK(64) and dev->dma_bus_mask = 0, so
>>>> min_not_zero(*dev->dma_mask, dev->bus_dma_mask) returns
>>>> DMA_BIT_MASK(64).
>>>>
>>>> Surely enough, if I hack dma_direct_possible() to return 0,
>>>> swiotlb_map() kicks in and the nvme driver starts working fine.
>>>>
>>>> I presume the question here is, why is dev->bus_dma_mask = 0 ?
>>>
>>> Because that's the default, and almost no code overrides that?
>>
>> But shouldn't drivers/of/device.c set that for the PCIe controller ?
> 
> Urgh, I really should have spotted the significance of "NVMe", but
> somehow it failed to click :(

Good thing it did now :-)

> Of course the existing code works fine for everything *except* PCI
> devices on DT-based systems... That's because of_dma_get_range() has
> never been made to work correctly with the trick we play of passing the
> host bridge of_node through of_dma_configure(). I've got at least 2 or 3
> half-finished attempts at improving that, but they keep getting
> sidetracked into trying to clean up the various new of_dma_configure()
> hacks I find in drivers and/or falling down the rabbit-hole of starting
> to redesign the whole dma_pfn_offset machinery entirely. Let me dig one
> up and try to constrain it to solve just this most common "one single
> limited range" condition for the sake of making actual progress...

That'd be nice, thank you. I'm happy to test it on various devices here.
Marek Vasut March 28, 2019, 3:25 a.m. UTC | #15
On 3/19/19 12:25 AM, Marek Vasut wrote:
> On 3/18/19 2:14 PM, Robin Murphy wrote:
>> On 17/03/2019 23:36, Marek Vasut wrote:
>>> On 3/17/19 11:29 AM, Geert Uytterhoeven wrote:
>>>> Hi Marek,
>>>
>>> Hi,
>>>
>>>> On Sun, Mar 17, 2019 at 12:04 AM Marek Vasut <marek.vasut@gmail.com>
>>>> wrote:
>>>>> On 3/16/19 10:25 PM, Marek Vasut wrote:
>>>>>> On 3/13/19 7:30 PM, Christoph Hellwig wrote:
>>>>>>> On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
>>>>>>>> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
>>>>>>>>> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
>>>>>>>>>>> Right, but whoever *interprets* the device masks after the
>>>>>>>>>>> driver has
>>>>>>>>>>> overridden them should be taking the (smaller) bus mask into
>>>>>>>>>>> account as
>>>>>>>>>>> well, so the question is where is *that* not being done
>>>>>>>>>>> correctly?
>>>>>>>>>>
>>>>>>>>>> Do you have a hint where I should look for that ?
>>>>>>>>>
>>>>>>>>> If this a 32-bit ARM platform it might the complete lack of support
>>>>>>>>> for bus_dma_mask in arch/arm/mm/dma-mapping.c..
>>>>>>>>
>>>>>>>> It's an ARM 64bit platform, just the PCIe controller is limited
>>>>>>>> to 32bit
>>>>>>>> address range, so the devices on the PCIe bus cannot read the host's
>>>>>>>> DRAM above the 32bit limit.
>>>>>>>
>>>>>>> arm64 should take the mask into account both for the swiotlb and
>>>>>>> iommu case.  What are the exact symptoms you see?
>>>>>>
>>>>>> With the nvme, the device is recognized, but cannot be used.
>>>>>> It boils down to PCI BAR access being possible, since that's all below
>>>>>> the 32bit boundary, but when the device tries to do any sort of DMA,
>>>>>> that transfer returns nonsense data.
>>>>>>
>>>>>> But when I call dma_set_mask_and_coherent(dev->dev,
>>>>>> DMA_BIT_MASK(32) in
>>>>>> the affected driver (thus far I tried this nvme, xhci-pci and ahci-pci
>>>>>> drivers), it all starts to work fine.
>>>>>>
>>>>>> Could it be that the driver overwrites the (coherent_)dma_mask and
>>>>>> that's why the swiotlb/iommu code cannot take this into account ?
>>>>>>
>>>>>>> Does it involve
>>>>>>> swiotlb not kicking in, or iommu issues?
>>>>>>
>>>>>> How can I check ? I added printks into arch/arm64/mm/dma-mapping.c and
>>>>>> drivers/iommu/dma-iommu.c , but I suspect I need to look elsewhere.
>>>>>
>>>>> Digging further ...
>>>>>
>>>>> drivers/nvme/host/pci.c nvme_map_data() calls dma_map_sg_attrs() and
>>>>> the
>>>>> resulting sglist contains entry with >32bit PA. This is because
>>>>> dma_map_sg_attrs() calls dma_direct_map_sg(), which in turn calls
>>>>> dma_direct_map_sg(), then dma_direct_map_page() and that's where it
>>>>> goes
>>>>> weird.
>>>>>
>>>>> dma_direct_map_page() does a dma_direct_possible() check before
>>>>> triggering swiotlb_map(). The check succeeds, so the later isn't
>>>>> executed.
>>>>>
>>>>> dma_direct_possible() calls dma_capable() with dev->dma_mask =
>>>>> DMA_BIT_MASK(64) and dev->dma_bus_mask = 0, so
>>>>> min_not_zero(*dev->dma_mask, dev->bus_dma_mask) returns
>>>>> DMA_BIT_MASK(64).
>>>>>
>>>>> Surely enough, if I hack dma_direct_possible() to return 0,
>>>>> swiotlb_map() kicks in and the nvme driver starts working fine.
>>>>>
>>>>> I presume the question here is, why is dev->bus_dma_mask = 0 ?
>>>>
>>>> Because that's the default, and almost no code overrides that?
>>>
>>> But shouldn't drivers/of/device.c set that for the PCIe controller ?
>>
>> Urgh, I really should have spotted the significance of "NVMe", but
>> somehow it failed to click :(
> 
> Good thing it did now :-)
> 
>> Of course the existing code works fine for everything *except* PCI
>> devices on DT-based systems... That's because of_dma_get_range() has
>> never been made to work correctly with the trick we play of passing the
>> host bridge of_node through of_dma_configure(). I've got at least 2 or 3
>> half-finished attempts at improving that, but they keep getting
>> sidetracked into trying to clean up the various new of_dma_configure()
>> hacks I find in drivers and/or falling down the rabbit-hole of starting
>> to redesign the whole dma_pfn_offset machinery entirely. Let me dig one
>> up and try to constrain it to solve just this most common "one single
>> limited range" condition for the sake of making actual progress...
> 
> That'd be nice, thank you. I'm happy to test it on various devices here.

Just curious, no stress, did you get anywhere with this patch(set) yet?
Marek Vasut April 9, 2019, 12:16 p.m. UTC | #16
On 3/28/19 4:25 AM, Marek Vasut wrote:
> On 3/19/19 12:25 AM, Marek Vasut wrote:
>> On 3/18/19 2:14 PM, Robin Murphy wrote:
>>> On 17/03/2019 23:36, Marek Vasut wrote:
>>>> On 3/17/19 11:29 AM, Geert Uytterhoeven wrote:
>>>>> Hi Marek,
>>>>
>>>> Hi,
>>>>
>>>>> On Sun, Mar 17, 2019 at 12:04 AM Marek Vasut <marek.vasut@gmail.com>
>>>>> wrote:
>>>>>> On 3/16/19 10:25 PM, Marek Vasut wrote:
>>>>>>> On 3/13/19 7:30 PM, Christoph Hellwig wrote:
>>>>>>>> On Sat, Mar 09, 2019 at 12:23:15AM +0100, Marek Vasut wrote:
>>>>>>>>> On 3/8/19 8:18 AM, Christoph Hellwig wrote:
>>>>>>>>>> On Thu, Mar 07, 2019 at 12:14:06PM +0100, Marek Vasut wrote:
>>>>>>>>>>>> Right, but whoever *interprets* the device masks after the
>>>>>>>>>>>> driver has
>>>>>>>>>>>> overridden them should be taking the (smaller) bus mask into
>>>>>>>>>>>> account as
>>>>>>>>>>>> well, so the question is where is *that* not being done
>>>>>>>>>>>> correctly?
>>>>>>>>>>>
>>>>>>>>>>> Do you have a hint where I should look for that ?
>>>>>>>>>>
>>>>>>>>>> If this a 32-bit ARM platform it might the complete lack of support
>>>>>>>>>> for bus_dma_mask in arch/arm/mm/dma-mapping.c..
>>>>>>>>>
>>>>>>>>> It's an ARM 64bit platform, just the PCIe controller is limited
>>>>>>>>> to 32bit
>>>>>>>>> address range, so the devices on the PCIe bus cannot read the host's
>>>>>>>>> DRAM above the 32bit limit.
>>>>>>>>
>>>>>>>> arm64 should take the mask into account both for the swiotlb and
>>>>>>>> iommu case.  What are the exact symptoms you see?
>>>>>>>
>>>>>>> With the nvme, the device is recognized, but cannot be used.
>>>>>>> It boils down to PCI BAR access being possible, since that's all below
>>>>>>> the 32bit boundary, but when the device tries to do any sort of DMA,
>>>>>>> that transfer returns nonsense data.
>>>>>>>
>>>>>>> But when I call dma_set_mask_and_coherent(dev->dev,
>>>>>>> DMA_BIT_MASK(32) in
>>>>>>> the affected driver (thus far I tried this nvme, xhci-pci and ahci-pci
>>>>>>> drivers), it all starts to work fine.
>>>>>>>
>>>>>>> Could it be that the driver overwrites the (coherent_)dma_mask and
>>>>>>> that's why the swiotlb/iommu code cannot take this into account ?
>>>>>>>
>>>>>>>> Does it involve
>>>>>>>> swiotlb not kicking in, or iommu issues?
>>>>>>>
>>>>>>> How can I check ? I added printks into arch/arm64/mm/dma-mapping.c and
>>>>>>> drivers/iommu/dma-iommu.c , but I suspect I need to look elsewhere.
>>>>>>
>>>>>> Digging further ...
>>>>>>
>>>>>> drivers/nvme/host/pci.c nvme_map_data() calls dma_map_sg_attrs() and
>>>>>> the
>>>>>> resulting sglist contains entry with >32bit PA. This is because
>>>>>> dma_map_sg_attrs() calls dma_direct_map_sg(), which in turn calls
>>>>>> dma_direct_map_sg(), then dma_direct_map_page() and that's where it
>>>>>> goes
>>>>>> weird.
>>>>>>
>>>>>> dma_direct_map_page() does a dma_direct_possible() check before
>>>>>> triggering swiotlb_map(). The check succeeds, so the later isn't
>>>>>> executed.
>>>>>>
>>>>>> dma_direct_possible() calls dma_capable() with dev->dma_mask =
>>>>>> DMA_BIT_MASK(64) and dev->dma_bus_mask = 0, so
>>>>>> min_not_zero(*dev->dma_mask, dev->bus_dma_mask) returns
>>>>>> DMA_BIT_MASK(64).
>>>>>>
>>>>>> Surely enough, if I hack dma_direct_possible() to return 0,
>>>>>> swiotlb_map() kicks in and the nvme driver starts working fine.
>>>>>>
>>>>>> I presume the question here is, why is dev->bus_dma_mask = 0 ?
>>>>>
>>>>> Because that's the default, and almost no code overrides that?
>>>>
>>>> But shouldn't drivers/of/device.c set that for the PCIe controller ?
>>>
>>> Urgh, I really should have spotted the significance of "NVMe", but
>>> somehow it failed to click :(
>>
>> Good thing it did now :-)
>>
>>> Of course the existing code works fine for everything *except* PCI
>>> devices on DT-based systems... That's because of_dma_get_range() has
>>> never been made to work correctly with the trick we play of passing the
>>> host bridge of_node through of_dma_configure(). I've got at least 2 or 3
>>> half-finished attempts at improving that, but they keep getting
>>> sidetracked into trying to clean up the various new of_dma_configure()
>>> hacks I find in drivers and/or falling down the rabbit-hole of starting
>>> to redesign the whole dma_pfn_offset machinery entirely. Let me dig one
>>> up and try to constrain it to solve just this most common "one single
>>> limited range" condition for the sake of making actual progress...
>>
>> That'd be nice, thank you. I'm happy to test it on various devices here.
> 
> Just curious, no stress, did you get anywhere with this patch(set) yet?

Bump ?

Patch
diff mbox series

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 021ce46e2e57..2acce056dd8c 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -926,6 +926,13 @@  static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 	if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
 		return 0;
 
+	/*
+	 * The upstream device could have applied DMA constraints already,
+	 * respect those and do not change the DMA masks.
+	 */
+	if (pdev->dev.dma_mask && pdev->dev.coherent_dma_mask)
+		return 0;
+
 	if (using_dac &&
 	    !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 		rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));