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[4/8] hw/southbridge: Add the PIIX3 chipset to Kconfig

Message ID 20190310235351.1863-5-philmd@redhat.com (mailing list archive)
State New, archived
Headers show
Series Kconfig: Clean up the PIIX southbridge devices | expand

Commit Message

Philippe Mathieu-Daudé March 10, 2019, 11:53 p.m. UTC 
The PIIX3 (Intel 82371SB) is a bridge between PCI <-> ISA.

It is an exhanced PIIX, thus contains the same features.
It also contains:
 - separate Master/Slave IDE mode
 - compliant to PCI rev 2.1 specifications
 - IOAPIC
 - USB UHCI (2 ports)
 - USB Legacy Support (emulated devices):
   - 8042 Keyboard Controller
   - A20-Gate

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/isa/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 681e6f1bce..f8494edd67 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -37,6 +37,15 @@  config PIIX
     #select NMI_PIIX
     select ISA_BUS
 
+config PIIX3
+    bool
+    select PIIX
+    #select PCI_PIIX3
+    #select IDE_PIIX3
+    select IOAPIC
+    select USB_UHCI
+    select I8042
+
 config PIIX4
     bool
     # For historical reasons, SuperIO devices are created in the board