| Message ID | 20190312231853.3150-1-laurent.pinchart+renesas@ideasonboard.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Kieran Bingham |
| Headers | show |
| Series | drm: rcar-du: lvds: Fix post-DLL divider calculation | expand |
Hi Laurent, Thank you for the patch, On 12/03/2019 23:18, Laurent Pinchart wrote: > The PLL parameters are computed by looping over the range of acceptable > M, N and E values, and selecting the combination that produces the > output frequency closest to the target. The internal frequency > constraints are taken into account by restricting the tested values for > the PLL parameters, reducing the search space. The target frequency, > however, is only taken into account when computing the post-PLL divider, > which can result in a 0 value for the divider when the PLL output > frequency being tested is lower than half of the target frequency. > Subsequent loops will produce a better set of PLL parameters, but for > some of the iterations this can result in a division by 0. > > Fix it by clamping the divider value. We could instead restrict the E > values being tested in the inner loop, but that would require additional > calculation that would likely be less efficient as the E parameter can > only take three different values. Sounds reasonable to me, and does prevent div/0, thus: Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > Fixes: c25c01361199 ("drm: rcar-du: lvds: D3/E3 support") > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > --- > drivers/gpu/drm/rcar-du/rcar_lvds.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c > index 7ef97b2a6eda..9f5ff1acab4e 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c > +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c > @@ -283,7 +283,7 @@ static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk, > * divider. > */ > fout = fvco / (1 << e) / div7; > - div = DIV_ROUND_CLOSEST(fout, target); > + div = max(1UL, DIV_ROUND_CLOSEST(fout, target)); > diff = abs(fout / div - target); > > if (diff < pll->diff) { >
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 7ef97b2a6eda..9f5ff1acab4e 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -283,7 +283,7 @@ static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk, * divider. */ fout = fvco / (1 << e) / div7; - div = DIV_ROUND_CLOSEST(fout, target); + div = max(1UL, DIV_ROUND_CLOSEST(fout, target)); diff = abs(fout / div - target); if (diff < pll->diff) {
The PLL parameters are computed by looping over the range of acceptable M, N and E values, and selecting the combination that produces the output frequency closest to the target. The internal frequency constraints are taken into account by restricting the tested values for the PLL parameters, reducing the search space. The target frequency, however, is only taken into account when computing the post-PLL divider, which can result in a 0 value for the divider when the PLL output frequency being tested is lower than half of the target frequency. Subsequent loops will produce a better set of PLL parameters, but for some of the iterations this can result in a division by 0. Fix it by clamping the divider value. We could instead restrict the E values being tested in the inner loop, but that would require additional calculation that would likely be less efficient as the E parameter can only take three different values. Fixes: c25c01361199 ("drm: rcar-du: lvds: D3/E3 support") Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> --- drivers/gpu/drm/rcar-du/rcar_lvds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)