| Message ID | 20190314223839.28258-5-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/5] drm/i915: Mark up vGPU support for full-ppgtt | expand |
On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote: > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8, > so refactor that into a common routine. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Bob Paauwe <bob.j.paauwe@intel.com> > Cc: Matthew Auld <matthew.william.auld@gmail.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 43 +++++++++++++---------------- > 1 file changed, 19 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 83362c8ac110..b8055c8d4e71 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1513,6 +1513,23 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt) > return -ENOMEM; > } > > +static void ppgtt_init(struct drm_i915_private *i915, > + struct i915_hw_ppgtt *ppgtt) > +{ > + kref_init(&ppgtt->ref); > + > + ppgtt->vm.i915 = i915; > + ppgtt->vm.dma = &i915->drm.pdev->dev; > + ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size); > + > + i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT); > + > + ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma; > + ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma; > + ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages; > + ppgtt->vm.vma_ops.clear_pages = clear_pages; > +} > + > /* > * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers > * with a net effect resembling a 2-level page table in normal x86 terms. Each > @@ -1529,17 +1546,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) > if (!ppgtt) > return ERR_PTR(-ENOMEM); > > - kref_init(&ppgtt->ref); > - > - ppgtt->vm.i915 = i915; > - ppgtt->vm.dma = &i915->drm.pdev->dev; > - ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size); > + ppgtt_init(i915, ppgtt); > > /* From bdw, there is support for read-only pages in the PPGTT. */ > ppgtt->vm.has_read_only = true; > > - i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT); > - > /* There are only few exceptions for gen >=6. chv and bxt. > * And we are not sure about the latter so play safe for now. > */ > @@ -1583,11 +1594,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) > > ppgtt->vm.cleanup = gen8_ppgtt_cleanup; > > - ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma; > - ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma; > - ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages; > - ppgtt->vm.vma_ops.clear_pages = clear_pages; > - > return ppgtt; > > err_scratch: > @@ -1979,24 +1985,13 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915) > if (!ppgtt) > return ERR_PTR(-ENOMEM); > > - kref_init(&ppgtt->base.ref); > - > - ppgtt->base.vm.i915 = i915; > - ppgtt->base.vm.dma = &i915->drm.pdev->dev; > - ppgtt->base.vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size); > - > - i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT); > + ppgtt_init(i915, &ppgtt->base); > > ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range; > ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range; > ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries; > ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup; > > - ppgtt->base.vm.vma_ops.bind_vma = ppgtt_bind_vma; > - ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma; > - ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages; > - ppgtt->base.vm.vma_ops.clear_pages = clear_pages; > - > ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode; > > err = gen6_ppgtt_init_scratch(ppgtt); > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Rodrigo Vivi (2019-03-14 22:53:44) > On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote: > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8, > > so refactor that into a common routine. > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Bob Paauwe <bob.j.paauwe@intel.com> > > Cc: Matthew Auld <matthew.william.auld@gmail.com> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> I've pushed this series so that 36 bits should be a nice and simple drop in. Thank you Bob for preparing these, sorry for not being clear enough on the direction I felt the patches should take. -Chris
On Fri, 15 Mar 2019 09:09:11 +0000 Chris Wilson <chris@chris-wilson.co.uk> wrote: > Quoting Rodrigo Vivi (2019-03-14 22:53:44) > > On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote: > > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8, > > > so refactor that into a common routine. > > > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > > Cc: Bob Paauwe <bob.j.paauwe@intel.com> > > > Cc: Matthew Auld <matthew.william.auld@gmail.com> > > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > I've pushed this series so that 36 bits should be a nice and simple drop > in. > > Thank you Bob for preparing these, sorry for not being clear enough on > the direction I felt the patches should take. > -Chris Thanks Chris, It was helpful to see how you organized and re-wrote the series. This was not code I was familiar with when I started so you're guidance helped a lot. Now I get to fix the EHL patches to take advantage of this. Bob > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote: > On Fri, 15 Mar 2019 09:09:11 +0000 > Chris Wilson <chris@chris-wilson.co.uk> wrote: > > > Quoting Rodrigo Vivi (2019-03-14 22:53:44) > > > On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote: > > > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8, > > > > so refactor that into a common routine. > > > > > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > > > Cc: Bob Paauwe <bob.j.paauwe@intel.com> > > > > Cc: Matthew Auld <matthew.william.auld@gmail.com> > > > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > I've pushed this series so that 36 bits should be a nice and simple drop > > in. > > > > Thank you Bob for preparing these, sorry for not being clear enough on > > the direction I felt the patches should take. > > -Chris > > Thanks Chris, Thanks a lot Chris. > > It was helpful to see how you organized and re-wrote the series. This > was not code I was familiar with when I started so you're guidance > helped a lot. > > Now I get to fix the EHL patches to take advantage of this. cool, so I will split the series into rv-b ones and probably push soon just leaving the ppgt_size one for you to rebase on top... thoughts? > > Bob > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > -- > -- > Bob Paauwe > Bob.J.Paauwe@intel.com > IOTG / PED Software Organization > Intel Corp. Folsom, CA > (916) 356-6193 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, 15 Mar 2019 10:01:51 -0700 Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote: > > On Fri, 15 Mar 2019 09:09:11 +0000 > > Chris Wilson <chris@chris-wilson.co.uk> wrote: > > > > > Quoting Rodrigo Vivi (2019-03-14 22:53:44) > > > > On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote: > > > > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8, > > > > > so refactor that into a common routine. > > > > > > > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > > > > Cc: Bob Paauwe <bob.j.paauwe@intel.com> > > > > > Cc: Matthew Auld <matthew.william.auld@gmail.com> > > > > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > > > > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > > > I've pushed this series so that 36 bits should be a nice and simple drop > > > in. > > > > > > Thank you Bob for preparing these, sorry for not being clear enough on > > > the direction I felt the patches should take. > > > -Chris > > > > Thanks Chris, > > Thanks a lot Chris. > > > > > It was helpful to see how you organized and re-wrote the series. This > > was not code I was familiar with when I started so you're guidance > > helped a lot. > > > > Now I get to fix the EHL patches to take advantage of this. > > cool, so I will split the series into rv-b ones and probably > push soon just leaving the ppgt_size one for you to rebase > on top... > > thoughts? Would it make more sense to drop Patch 8, drm/i915/ehl: ehl has only 36bit extended ppgtt support and update patch 1 with the size added to the device_info? Otherwise, patch 8 becomes just adding the size into the device_info. Either way works for me. > > > > > Bob > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > -- > > -- > > Bob Paauwe > > Bob.J.Paauwe@intel.com > > IOTG / PED Software Organization > > Intel Corp. Folsom, CA > > (916) 356-6193 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Mar 15, 2019 at 10:26:04AM -0700, Bob Paauwe wrote: > On Fri, 15 Mar 2019 10:01:51 -0700 > Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > > > On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote: > > > On Fri, 15 Mar 2019 09:09:11 +0000 > > > Chris Wilson <chris@chris-wilson.co.uk> wrote: > > > > > > > Quoting Rodrigo Vivi (2019-03-14 22:53:44) > > > > > On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote: > > > > > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8, > > > > > > so refactor that into a common routine. > > > > > > > > > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > > > > > Cc: Bob Paauwe <bob.j.paauwe@intel.com> > > > > > > Cc: Matthew Auld <matthew.william.auld@gmail.com> > > > > > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > > > > > > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > > > > > I've pushed this series so that 36 bits should be a nice and simple drop > > > > in. > > > > > > > > Thank you Bob for preparing these, sorry for not being clear enough on > > > > the direction I felt the patches should take. > > > > -Chris > > > > > > Thanks Chris, > > > > Thanks a lot Chris. > > > > > > > > It was helpful to see how you organized and re-wrote the series. This > > > was not code I was familiar with when I started so you're guidance > > > helped a lot. > > > > > > Now I get to fix the EHL patches to take advantage of this. > > > > cool, so I will split the series into rv-b ones and probably > > push soon just leaving the ppgt_size one for you to rebase > > on top... > > > > thoughts? > > Would it make more sense to drop Patch 8, drm/i915/ehl: ehl has only > 36bit extended ppgtt support and update patch 1 with the size added to the > device_info? > > Otherwise, patch 8 becomes just adding the size into the device_info. of course! Unfortunately I read the email after I sent the rv-b patches for CI... But I will change it there and send a v2 on top. > > Either way works for me. > > > > > > > > > Bob > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > > > > -- > > > -- > > > Bob Paauwe > > > Bob.J.Paauwe@intel.com > > > IOTG / PED Software Organization > > > Intel Corp. Folsom, CA > > > (916) 356-6193 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > -- > Bob Paauwe > Bob.J.Paauwe@intel.com > IOTG / PED Software Organization > Intel Corp. Folsom, CA > (916) 356-6193 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 83362c8ac110..b8055c8d4e71 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1513,6 +1513,23 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt) return -ENOMEM; } +static void ppgtt_init(struct drm_i915_private *i915, + struct i915_hw_ppgtt *ppgtt) +{ + kref_init(&ppgtt->ref); + + ppgtt->vm.i915 = i915; + ppgtt->vm.dma = &i915->drm.pdev->dev; + ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size); + + i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT); + + ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma; + ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma; + ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages; + ppgtt->vm.vma_ops.clear_pages = clear_pages; +} + /* * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers * with a net effect resembling a 2-level page table in normal x86 terms. Each @@ -1529,17 +1546,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) if (!ppgtt) return ERR_PTR(-ENOMEM); - kref_init(&ppgtt->ref); - - ppgtt->vm.i915 = i915; - ppgtt->vm.dma = &i915->drm.pdev->dev; - ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size); + ppgtt_init(i915, ppgtt); /* From bdw, there is support for read-only pages in the PPGTT. */ ppgtt->vm.has_read_only = true; - i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT); - /* There are only few exceptions for gen >=6. chv and bxt. * And we are not sure about the latter so play safe for now. */ @@ -1583,11 +1594,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) ppgtt->vm.cleanup = gen8_ppgtt_cleanup; - ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma; - ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma; - ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages; - ppgtt->vm.vma_ops.clear_pages = clear_pages; - return ppgtt; err_scratch: @@ -1979,24 +1985,13 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915) if (!ppgtt) return ERR_PTR(-ENOMEM); - kref_init(&ppgtt->base.ref); - - ppgtt->base.vm.i915 = i915; - ppgtt->base.vm.dma = &i915->drm.pdev->dev; - ppgtt->base.vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size); - - i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT); + ppgtt_init(i915, &ppgtt->base); ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range; ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range; ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries; ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup; - ppgtt->base.vm.vma_ops.bind_vma = ppgtt_bind_vma; - ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma; - ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages; - ppgtt->base.vm.vma_ops.clear_pages = clear_pages; - ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode; err = gen6_ppgtt_init_scratch(ppgtt);
The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8, so refactor that into a common routine. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Bob Paauwe <bob.j.paauwe@intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 43 +++++++++++++---------------- 1 file changed, 19 insertions(+), 24 deletions(-)