arm64: dts: rockchip: Add nanopi4 ethernet phy
diff mbox series

Message ID 93a1654c1a905795d6cfff214379b68158ec4d3f.1552611930.git.robin.murphy@arm.com
State New
Headers show
Series
  • arm64: dts: rockchip: Add nanopi4 ethernet phy
Related show

Commit Message

Robin Murphy March 15, 2019, 1:05 a.m. UTC
The nanopi4 boards have the INTB pin of the RTL8211E phy wired up, so we
can make use of that and avoid having to poll for line status changes.
Apparently RTL8211E only requires 30ms of post-reset delay, so we may as
well save a little bit of time there as well.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 .../boot/dts/rockchip/rk3399-nanopi4.dtsi     | 27 +++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

Comments

Heiko Stübner March 16, 2019, 7:50 p.m. UTC | #1
Am Freitag, 15. März 2019, 02:05:30 CET schrieb Robin Murphy:
> The nanopi4 boards have the INTB pin of the RTL8211E phy wired up, so we
> can make use of that and avoid having to poll for line status changes.
> Apparently RTL8211E only requires 30ms of post-reset delay, so we may as
> well save a little bit of time there as well.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

applied for 5.2

Thanks
Heiko

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index d325e117287b..dd16c80d923e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -148,15 +148,28 @@ 
 	assigned-clocks = <&cru SCLK_RMII_SRC>;
 	clock_in_out = "input";
 	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>;
+	pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+	phy-handle = <&rtl8211e>;
 	phy-mode = "rgmii";
 	phy-supply = <&vcc3v3_s3>;
 	snps,reset-active-low;
-	snps,reset-delays-us = <0 10000 50000>;
+	snps,reset-delays-us = <0 10000 30000>;
 	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
 	tx_delay = <0x28>;
 	rx_delay = <0x11>;
 	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211e: phy@1 {
+			reg = <1>;
+			interrupt-parent = <&gpio3>;
+			interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
 };
 
 &gpu {
@@ -481,6 +494,16 @@ 
 		};
 	};
 
+	phy {
+		phy_intb: phy-intb {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rstb: phy-rstb {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	pmic {
 		cpu_b_sleep: cpu-b-sleep {
 			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;